Principal Design Engineer - High-Speed Interconnect

Job Title

Principal Design Engineer - High-Speed Interconnect

Role Summary

Lead the microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink) across multiple silicon products. Own designs from architectural requirements through RTL, synthesis readiness, verification support, and final delivery.

Work on a cross-functional team with architecture, verification, performance, firmware, physical design and implementation groups. Role is hybrid: team members are expected to be in the Austin office at least two days per week.

Experience Level

Senior — Principal-level role. Prefer candidates with 8+ years of experience in RTL design, microarchitecture, subsystem integration, or related semiconductor engineering roles.

Responsibilities

Core responsibilities include ownership of microarchitecture and hands-on RTL delivery for interconnect subsystems, cross-team collaboration, and technical leadership.

• Own microarchitecture, synthesizable RTL, interfaces, register definitions, and integration for high-speed interconnects (PCIe, CXL, UALink).
• Drive development from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery.
• Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets.
• Analyze workloads, traffic patterns, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation trade-offs.
• Lead technical design reviews, debug cross-functional issues, improve design and delivery methodologies, and mentor junior engineers.

Requirements

Must-have technical skills and experience.

• 8+ years of industry experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.
• Hands-on SystemVerilog experience developing sophisticated, high-performance digital subsystems.
• Deep practical knowledge of PCIe, CXL, and UALink protocol behavior, transaction flows, ordering, flow control, retries, error handling, and host/device integration.
• Experience with coherent and non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems.
• Familiarity with AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, and backpressure.
• Experience with CDC/RDC, reset sequencing, low-power design, lint, X-propagation, formal verification, synthesis, timing analysis, and waveform debug.
• Ability to convert architectural requirements into clear microarchitecture specifications and high-quality RTL.
• Proven technical leadership, communication, and delivery skills across multifunctional teams.

Nice-to-have:

• Experience with PCIe Gen6 or later, CXL 2.0 or later, UALink, chiplets, or die-to-die connectivity.
• Knowledge of RAS, IDE, TDISP, security, memory pooling, CXL.cache and CXL.mem, and accelerator connectivity.
• Experience integrating third-party IP, PHYs, firmware-visible capabilities, PCIe configuration space, BARs, interrupts, and error-management features.
• Proven track record delivering complex RTL or subsystem builds on schedule while meeting functional, performance, power, area, and quality targets.

Education Requirements

Bachelor's or Master's degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.