Principal Design Engineer – High-Speed Interconnect
ArmJob Title
Principal Design Engineer – High-Speed Interconnect
Role Summary
Lead microarchitecture and RTL implementation of high-speed interconnect subsystems (PCIe, CXL, UALink) across multiple silicon products. Work across architecture, verification, firmware, physical design and implementation teams to meet functional, performance, power, area and timing targets.
This is a hands-on senior engineering role focused on delivering synthesizable RTL, subsystem integration, and debug support while mentoring other engineers.
Experience Level
Senior — expects experienced engineers. The posting indicates 8+ years of relevant semiconductor or RTL subsystem experience.
Responsibilities
Primary responsibilities include owning design and delivery of interconnect subsystems and coordinating cross-functional integration.
- Define microarchitecture, interfaces, registers and implementation-ready RTL for high-speed interconnect subsystems.
- Drive designs from concept through RTL development, synthesis preparation, integration and delivery.
- Collaborate with architecture, verification, firmware, physical design and implementation teams to meet bandwidth, latency, power and timing goals.
- Analyze traffic patterns, buffer requirements, flow control and queue depths to guide design trade-offs.
- Lead technical reviews, debug cross-functional issues, and improve development methodologies and infrastructure.
- Mentor and provide technical leadership to other engineers on the team.
Requirements
Must-have technical skills and demonstrated delivery ability.
- Hands-on expertise in SystemVerilog and development of high-performance digital subsystems.
- Deep understanding of PCIe, CXL and UALink protocol behavior (transaction flows, ordering, flow control, retries, error handling, host/device integration, memory expansion and coherence).
- Experience with coherent or non-coherent interconnects, cache hierarchies, memory systems and high-speed I/O subsystems.
- Strong knowledge of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling and backpressure.
- Experience with CDC/RDC issues, reset sequencing, low-power design, linting, X-propagation, formal verification, synthesis, timing analysis and waveform debug.
- Proven technical leadership, cross-team communication and on-schedule delivery of complex RTL or subsystem designs.
Education Requirements
Bachelor's or Master's degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science or a related technical field.
About the Company
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
