Principal Design Engineer – High-Speed Interconnect

Job Title

Principal Design Engineer – High-Speed Interconnect

Role Summary

Lead the microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink) across multiple silicon products. Own implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, and drive delivery to meet functional, performance, power, area, and timing targets.

Experience Level

Senior — 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.

Responsibilities

Primary responsibilities include ownership of design, delivery, and cross-functional coordination for high-speed interconnect subsystems.

• Own microarchitecture, RTL development, and integration for PCIe, CXL, and UALink subsystems across silicon products.
• Translate system and protocol requirements into microarchitecture specs, interfaces, register definitions, and synthesizable RTL.
• Drive development from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery.
• Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet bandwidth, latency, power, area, and timing targets.
• Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation trade-offs.
• Lead technical reviews, debug cross-functional issues, improve development methodologies, and mentor engineers.

Requirements

The following are must-have technical skills and experience. Nice-to-have items follow separately.

• 8+ years of hands-on experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.
• Deep practical expertise in SystemVerilog and development of high-performance digital subsystems.
• Deep protocol-level understanding of PCIe, CXL, and UALink (transaction flows, ordering, flow control, retries, error handling, host/device integration, memory expansion, coherent connectivity).
• Experience with coherent or non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems.
• Strong knowledge of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, and backpressure handling.
• Experience with CDC/RDC, reset sequencing, low-power design flows, lint, X-propagation, formal verification, synthesis, timing analysis, and waveform debug.
• Ability to convert architectural requirements into clear microarchitecture documents and high-quality RTL.
• Proven technical leadership, communication, and cross-functional delivery skills.

Nice-to-have:

• Experience with PCIe Gen6 or later, CXL 2.0 or later, UALink, chiplets, or die-to-die connectivity.
• Familiarity with RAS, IDE, TDISP, security, memory pooling, CXL.cache, CXL.mem, and accelerator connectivity.
• Experience integrating third-party IP, PHYs, firmware-visible capabilities, PCIe configuration space, BARs, interrupts, and error-management features.
• Track record of delivering complex RTL/subsystem builds on schedule while meeting functional and performance targets.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; or equivalent practical experience.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.