Principal Design Engineer, HBM Architecture

Job Title

Principal Design Engineer, HBM Architecture

Role Summary

The HBM Architecture team designs datapath solutions for next-generation High Bandwidth Memory (HBM) products. This role architects and delivers logic-die and core-die datapath circuitry from concept through silicon bring-up and production, working closely with PHY, ECC, verification, layout, and system teams.

Experience Level

Level: Senior. Expected experience aligns with the posted qualifications (see Education Requirements for degree/years guidance); technical hands-on experience in high-speed datapath design is required.

Responsibilities

Design and deliver high-speed, reliable datapath architectures for HBM products and collaborate across functional teams.

• Architect and design HBM read/write datapath across core and logic die, including alignment, buffering, timing, and control logic.
• Develop high-speed, low-latency datapath circuits for multi-channel HBM and wide internal buses.
• Optimize designs for bandwidth, power, area, and timing closure at advanced process nodes.
• Design and integrate data reliability features (parity, ECC hooks, lane redundancy, remapping).
• Collaborate with PHY, DFT, verification, layout, and system teams to translate specifications into robust micro-architectures and ensure manufacturability and testability.
• Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies.
• Contribute to design reviews, documentation, silicon bring-up, and mentor engineers across HBM programs.
• Leverage AI tools to increase efficiency in regular engineering tasks where appropriate.

Requirements

Must-have technical skills and experience for immediate contribution.

• 3+ years experience in high-speed digital datapath design (memory, SerDes, or SoC datapath).
• 2+ years hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.
• Proven experience collaborating across PHY, verification, layout, and system teams to deliver silicon-quality designs.
• Experience optimizing designs for timing closure, power, and area at advanced nodes.
• Strong debugging, documentation, and design-review skills; ability to mentor engineers.

Nice-to-have:

• Understanding of HBM/DRAM read/write flow, timing, and multi-channel operation.
• Layout and floorplanning knowledge for high-speed datapaths.
• Experience with static timing analysis (STA) and timing-closure methodologies.
• Familiarity with signal integrity, skew control, and power optimization challenges at advanced process nodes.

Education Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 7+ years of relevant industry experience, or a Master’s degree with 5+ years of relevant industry experience. Fields explicitly referenced: Electrical Engineering and Computer Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.