Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Principal Design Engineer on the Analog & Mixed-Signal/SerDes design team working on die-to-die (D2D) products. The role leads circuit-level design, verification, and collaboration with layout and system architects to deliver high-speed I/O and SERDES analog blocks for advanced process nodes.

Experience Level

Senior — typically requires 8+ years of CMOS analog/mixed-signal IC design experience, with substantial experience in SERDES or high-speed I/O design.

Responsibilities

Provide technical leadership in analog/mixed-signal and SERDES circuit design across development from concept to silicon verification.

• Design high-speed D2D and SERDES products for industry-standard data rates on leading-edge nodes (example: 3nm FinFET).
• Develop analog/mixed-signal IC circuit blocks from specification through final verification against customer requirements.
• Collaborate with Layout Design Engineers on IC circuit blocks and PMA sections to ensure layout and physical constraints are met.
• Work with technical team leads on circuit design decisions and SERDES architectures.
• Coordinate with global teams across multiple time zones for design reviews, integration, and verification.

Requirements

Must-have technical skills and experience; a short list of preferred qualifications follows.

• Minimum 8 years of CMOS analog/mixed-signal design experience, preferably in SERDES or high-speed I/O.
• Strong understanding of jitter, signal equalization techniques, and high-speed signaling fundamentals.
• Design experience with SERDES circuit blocks such as Driver, Receiver, Serializer, Deserializer, Phase Interpolator, low-jitter PLLs, high-speed clock distribution, bias and bandgap, and voltage regulators.
• Proficiency with CAD tools for circuit simulation, layout iteration, and physical verification.
• Excellent problem-solving skills, analog aptitude, clear communication, and ability to work in multidisciplinary teams.
• Nice-to-have: experience with Cadence tools, lab test and silicon evaluation experience, design at >10 Gbps, and experience in sub-16 nm technologies.

Education Requirements

Minimum degree: BEng, MEng, or PhD, or equivalent practical experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.