Principal Design Engineer
Cadence Design SystemsJob Title
Principal Design Engineer
Role Summary
Senior DFT engineer responsible for defining and implementing SoC-level DFT architecture and flows across pre-silicon and post-silicon stages. The role works within a small engineering team and regularly collaborates with RTL, verification, physical design, operations, and multiple business units.
Experience Level
Senior. Typical background includes multiple years of industry experience; the posting specifies substantial experience expectations and at least three years of hands-on SoC DFT experience.
Responsibilities
Deliver DFT architecture and implementation for large, complex SoC designs and support silicon bring-up.
- Define and implement SoC-level DFT architecture for large, complex designs.
- Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG flows.
- Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
- Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
- Support post-silicon debug, failure analysis and yield learning.
- Collaborate with RTL, verification, physical design, operations, and cross-functional teams.
Requirements
Key technical and practical requirements. Degrees and formal education requirements are summarized in the Education Requirements section below.
- At least 3 years of hands-on SoC DFT experience.
- Strong expertise in SCAN, ATPG, and MBIST methodologies.
- Experience with pre-silicon validation and post-silicon debug and failure analysis.
- Strong problem solving and debugging skills.
- Ability to work effectively in a cross-functional engineering environment.
Nice-to-have:
- Scripting experience (TCL, Perl, Python) for flow automation and analysis.
- Experience with IP-level DFT integration and reuse.
- Exposure to low-power DFT considerations and complex clocking architectures.
- Familiarity with manufacturing test flows and silicon yield improvement.
Education Requirements
BS with a minimum of 7 years of experience, OR MS with a minimum of 5 years of experience, OR PhD with a minimum of 1 year of experience (as stated in the posting). Specific fields of study were not specified. No certifications were listed.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
