Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Join a team developing extremely high-speed wireline communications transceivers in CMOS. The role focuses on numerical modeling and architecture to guide selection and specification of transceiver components using mathematical and computer modeling.

The engineer will collaborate with analog and digital designers, applications engineers, and product specialists to evaluate trade-offs, drive end-to-end system performance, and support lab characterization of realized designs.

Experience Level

Senior-level. No specific years-of-experience requirement provided.

Responsibilities

The primary responsibilities center on modeling, architecture, and system-level verification for high-speed transceivers.

• Develop mathematical and computational models to specify and evaluate transceiver components and subsystems.
• Perform system-level analysis to identify bottlenecks, trade-offs, and performance limits.
• Collaborate with analog/digital designers and applications teams to translate system requirements into component specifications.
• Create and run simulations for design validation and data analysis.
• Support lab characterization, analyze measurement data, and reconcile models with silicon results.
• Contribute to architecture decisions that impact overall transceiver performance and integration.

Requirements

Core technical skills and abilities required for the role.

• Strong mathematical skills, especially linear systems (Fourier analysis, filter theory).
• Deep knowledge of communication systems fundamentals and signal propagation physics.
• Strong coding skills for simulation, modeling, and data analysis (e.g., MATLAB, Python, C++ or equivalent).
• Familiarity with signal processing (DSP) algorithms and architectures.
• Practical experimental and lab characterization skills; ability to design and execute measurements.
• Working knowledge of basic analog/digital circuits relevant to transceiver design.
• Ability to reason about systems end-to-end and identify performance bottlenecks.
• Proven ability to learn new technical areas independently and collaborate across disciplines.

Nice-to-have:

• Experience specifically with high-speed wireline transceivers and CMOS implementation.

Education Requirements

Preferably a PhD in mathematical or physical sciences (example fields mentioned: mathematics, physics, or related disciplines). No other specific degree or field-of-study requirements are stated.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.