Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Senior IC design engineer responsible for leading design and verification of high-speed I/O and datapath blocks. The role drives AI-first engineering practices to accelerate exploration, verification, and workflow automation while mentoring teams and working across integration, design, and applications groups.

Experience Level

Senior — minimum 8+ years of integrated circuit design experience (per hire expectations in the posting).

Responsibilities

Core responsibilities include technical ownership, driving AI-enabled workflows, and cross-functional collaboration:

• Design and verify major I/O and datapath blocks (receivers, serializers, clock distribution, equalizers, calibration, training, waveform pipelines) to meet performance and reliability targets.
• Adopt and champion AI-first engineering: deploy LLMs, code/RTL generation, prompt libraries, agents, and automation scripts to reduce manual patterns and cycle time.
• Redesign specifications, simulation, review, and verification workflows to be AI-consumable; build and maintain AI toolchains that integrate with EDA flows.
• Collaborate with integration, layout, verification, and applications teams to define interfaces, reconcile specifications, and quantify architectural trade-offs.
• Lead pilots, document methodology, and teach engineers AI-augmented design and verification practices.
• Drive physical design considerations including layout optimization, floor planning, and parasitic-aware design decisions.

Requirements

Must-have technical skills and experience:

• Hands-on experience using AI tools (LLM assistants, coding copilots, agentic workflows, ML-based EDA) with concrete examples of productivity or design impact.
• Proven experience restructuring workflows for AI operation and building custom prompts/agents for automation.
• Deep understanding of high-speed I/O performance, power/area trade-offs, and chip architecture implications.
• Experience with physical design flows, layout optimization, and parasitic extraction.

Nice-to-have / preferred:

• Built or deployed custom AI agents, LLM pipelines, or ML models applied to IC design, verification, layout, or debug; familiarity with prompt engineering, RAG, or fine-tuning.
• Quantified productivity improvements from AI-driven changes (cycle time, defect reduction, coverage gains).
• Experience with DRAM and high-speed interfaces (DDR4/5, LPDDR5/6, HBM3/4) and deep CMOS device/BSIM knowledge.

Education Requirements

BS or MS in Electrical Engineering (specified). The posting requires 8+ years of IC design experience alongside the degree requirement.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.