Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Lead development, layout, and optimization of datapath and high-speed I/O circuits for next-generation NAND flash memory in the NVEG team. Drive architectural decisions to meet aggressive data-rate, power, and area targets while embedding AI-enabled methods into the design lifecycle.

Experience Level

Senior — requires substantial senior-level IC design experience (posting indicates 8+ years of relevant experience).

Responsibilities

Technical and team leadership focused on AI-augmented design workflows and high-performance IO/datapath blocks.

• Use AI tools daily to accelerate design exploration, layout iteration, verification, and documentation.
• Redesign design, verification, and debug workflows so AI is a first-class participant (prompt libraries, agents, script automation, AI-consumable specs).
• Evaluate and pilot AI/ML tools, publish internal methodologies, and drive team adoption to reduce cycle time and improve quality.
• Design, verify, and optimize major IO/datapath blocks (input receivers, serializers/deserializers, clock distribution, equalizers, calibration, training features, wave pipelines).
• Collaborate across functions to define interfaces, reconcile specifications, and align designs with system and customer requirements.
• Mentor engineers on AI-first workflows, present results to expert panels, and document AI-augmented methodologies.

Requirements

Must-have technical skills, hands-on AI usage, and demonstrated process leadership.

• Demonstrated, hands-on use of AI tools (LLM assistants, coding copilots, agentic workflows, or ML-based EDA aids) incorporated into routine engineering work.
• Proven ability to redesign or create engineering workflows around AI capabilities (restructuring specs, review flows, verification pipelines; building prompts, scripts, or agents).
• Deep knowledge of high-speed IO circuit performance, power/area optimization, and top-level chip architecture/floorplanning.
• Proven track record in physical design flows, layout optimization, and parasitic extraction.
• Strong collaboration and communication skills for multi-functional integration and customer alignment.
• Growth mindset toward continuous learning of AI tools and methods.

Nice-to-have:

• Experience building or deploying custom AI agents, LLM pipelines, or ML models for IC design, verification, layout, or silicon debug.
• Familiarity with prompt engineering, retrieval-augmented generation (RAG), fine-tuning, or agentic frameworks applied to engineering workflows.
• Experience quantifying productivity or quality impacts from AI-driven workflow changes.
• Experience with industry-standard high-speed interfaces (e.g., DDR, LPDDR, HBM) or comprehensive CMOS device physics and reliability knowledge.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or a related technical field is stated as preferred; equivalent practical experience is acceptable. The posting indicates this role expects senior-level experience (8+ years) in IC design.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.