Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Principal-level IC design engineer responsible for designing and verifying high-speed IO and datapath blocks and for driving AI-first engineering practices across the team. The role combines technical ownership of complex analog/digital interfaces with leadership in workflow automation, verification, and cross-functional integration.

Experience Level

Senior — requires 8+ years of IC design experience.

Responsibilities

Deliver design, verification, and process improvements for high-speed interfaces and lead AI-enabled engineering workflows.

• Design and verify major IO/datapath blocks (receivers, serializers, clock distribution, equalizers, calibration, training, and waveform pipelines) to meet performance targets.
• Adopt and embed AI-first tooling (LLM assistants, code/RTL generation, agents, ML-based EDA) to automate recurring engineering tasks.
• Redesign specs, simulations, reviews, and hand-offs to be AI-consumable and build prompt libraries, scripts, and agents that reduce manual work.
• Run pilots and evaluate emerging AI tools; publish standard methodologies that reduce cycle time or improve quality.
• Collaborate with integration, design, and applications teams to define interfaces, reconcile specifications, and quantify trade-offs.
• Mentor engineers on AI-augmented workflows and document reproducible, team-wide practices.

Requirements

Key required and preferred qualifications for successful candidates.

• Must-have: Hands-on experience using AI tools (LLM assistants, coding copilots, agentic workflows, ML-based EDA) with demonstrable impact on productivity or design outcomes.
• Must-have: Experience reorganizing engineering workflows for AI consumption (spec restructuring, verification rework, building custom prompts/agents).
• Must-have: Deep understanding of high-speed IO performance, power/area trade-offs, and chip architecture/floorplanning.
• Must-have: Experience with physical design flows, layout optimization, and parasitic extraction.
• Nice-to-have: Built or deployed custom AI agents, LLM pipelines, or ML models for IC design, verification, layout, or debug.
• Nice-to-have: Quantified metrics showing AI-driven productivity gains (cycle time, defect reduction, coverage improvements).
• Nice-to-have: DRAM or other high-speed interface experience (DDR4/5, LPDDR5/6, HBM3/4) and deep CMOS device physics / BSIM modeling knowledge.

Education Requirements

BS or MS in Electrical Engineering (specified in the minimum qualifications).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.