Principal Design Engineer
Design and maintain system-level memory IP models (SDRAM, NAND Flash, eMMC, SD Card, DFI, UFS) for hardware-based verification products. Serve as an individual contributor responsible for RTL design, verification, productization, documentation, and customer-facing technical support within a cross-functional team.
Senior β requires a minimum of 5 years of relevant experience.
Key responsibilities include:
Must-have and preferred skills:
Master's degree in Electrical Engineering (MSEE) or equivalent; the posting specifies MSEE or equivalent with a minimum of 5 years of significant experience designing complex protocols or hardware systems. Equivalent practical experience is acceptable.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
