Principal Design Engineer
Design and lead high-speed memory IP development (GDDR7, DDR5, LPDDR6) with a focus on analog circuitry. Serve as a strong individual contributor across analog design, layout, digital integration, documentation, and silicon validation.
Expect to drive designs from specification through silicon characterization and participate in customer-facing technical discussions.
Senior; typically requires 5+ years of relevant experience.
Core responsibilities include leading IP development and delivering analog IPs through full development cycles.
Must-have skills and experience for the role.
Posting specifies engineering degrees: B.Tech / BE / ME / M.Tech.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
