Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Lead micro-architecture, RTL and HW/SW co-design for high-performance SoC component IP, with primary focus on ultra-dense SRAM memory compilers. You will be part of the Central Engineering digital team supporting multiple product groups and external customers.

Experience Level

Senior — typical experience ranges: 12–17 years with a Bachelor’s degree, or 7–12 years with a Master’s/PhD (per employer guidance).

Responsibilities

Accountable for end-to-end frontend design and delivery of timing- and performance-critical IP and SoC components.

• Lead micro-architecture and RTL development for SoC components (memory controllers, PCIe/CXL interfaces, SRAM compilers).
• Drive HW/SW co-design and collaborate with architects, verification, physical design and system teams.
• Deliver timing closure, power optimization, and quality production-ready RTL on aggressive schedules.
• Perform RTL quality checks and sign-off coordination with verification teams.
• Mentor engineers and contribute to technical roadmaps and design reviews.

Requirements

Technical must-haves and preferred skills.

• Strong understanding of SoC architecture, processor cores, memory subsystems and peripheral interfaces; prior SoC integration experience.
• Extensive experience in Verilog and/or VHDL and RTL implementation practices.
• Familiarity with static analysis and lint/CDC flows (Spyglass, LINT, CDC checks).
• Proficient scripting skills for automation (Perl, Python).
• Proven record of delivering production-quality designs under tight schedules.
• Domain expertise in CXL/PCIe protocols and DDR memory controllers is a plus.
• Ability to work across cross-functional teams and coordinate design handoffs (architecture, verification, timing, power).
• May require eligibility to access export-controlled technology; applicants may be subject to export license review.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or related field (listed experience guidance: 12–17 years). Alternatively, Master’s degree or PhD in Computer Science, Electrical Engineering, or related field (listed experience guidance: 7–12 years).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.