Principal Design Engineer
Cadence Design SystemsJob Title
Principal Design Engineer
Role Summary
Lead analog/mixed-signal design for high-speed interface and memory IP (UCIe, D2D, PCIe, DDR/LPDDR, HBM, GDDR, SerDes) on advanced process nodes. Coordinate across Analog, Layout, AMS verification, Digital, and Physical Design to deliver IP from architecture to silicon.
Preferred work locations: Hyderabad (preferred), Noida, Pune.
Experience Level
Senior — 10–17+ years of relevant industry experience in analog/high-speed interface IP design.
Responsibilities
Primary responsibilities include architecture, design, integration, and delivery of high-speed analog/AMS IPs and leading cross-functional programs.
- Architect and design high-speed TX/RX, PLL, DLL, CDR, clocking, datapath, I/O, and interface circuits.
- Drive design closure for performance, power, area, jitter, and timing.
- Lead complex IP programs with Analog Design, Layout, AMS Verification, Digital, and Physical Design teams.
- Mentor engineers and establish technical direction, design methodologies, and best practices.
- For management roles: manage project execution, staffing, risk, scheduling, and customer technical engagements.
Requirements
Must-have technical skills and experience.
- Proven expertise in high-speed interface design: UCIe / Die-to-Die (D2D), PCIe Gen3–Gen6, DDRx / LPDDRx / GDDRx / HBM, and high-speed SerDes architectures.
- Strong analog design and I/O fundamentals, including jitter and timing analysis.
- Knowledge of SI/PI, ESD, reliability, and PPA optimization.
- Demonstrated track record delivering complex IPs from architecture through silicon bring-up.
- Excellent communication, leadership, and problem-solving skills; ability to lead technical teams.
Nice-to-have:
- Experience with advanced process nodes (16nm, 12nm, 10nm, 7nm, 5nm, 3nm).
- Experience in IP architecture, technology migration, and design reuse methodologies.
- Proven leadership delivering high-performance connectivity or memory interface solutions for AI, HPC, networking, or data-center applications.
Education Requirements
BE / B.Tech / ME / M.Tech / MS (as listed). Fields not specified; typically engineering disciplines related to analog/IC design or electrical/electronics engineering.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
