Job Title
Principal Design Automation Engineer
Role Summary
Drive NAND circuit development by delivering design automation, agentic circuit-design enablement, and environment transition within the NVE Design Engineering organization. Integrate core block schematics into full-chip designs and validate performance using industry simulators.
Experience Level
Senior β minimum 8+ years of NAND design-relevant experience.
Responsibilities
Primary responsibilities include circuit design, automation enablement, and cross-functional integration to reduce cycle time and improve verification reliability.
- Implement core Xpath, Ypath and Array block designs and integrate them into full-chip schematics; validate via block and chip-level simulations.
- Design analog and mixed-signal circuits and layouts (page buffers, block selectors, X/Y decoders, bias/waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, regulators, oscillators, bandgap, IO buffers, RTL/Verilog) and validate performance with simulation.
- Serve as a technical authority solving issues at the intersection of circuit behavior, modeling, simulation methodology, and automation reliability.
- Develop and productize agentic/AI-assisted enablement for circuit design: environment setup and self-healing configuration, guided simulation and debug, intelligent corner planning and coverage closure, automated schematic/layout checks, documentation synthesis, and knowledge retrieval.
- Provide reproducible verification run recipes, golden reference management, and regression gating for analog/mixed-signal verification.
- Integrate automation with project execution and partner with circuit designers, firmware, validation, and architecture teams to deliver measurable cycle-time reductions.
- Collaborate with cross-functional teams (product engineering, test, probe, process integration, assembly, marketing) to support manufacturability, testability, reliability, and time-to-market.
Requirements
Must-have technical skills and experience for day-one impact; concise list of preferred additions.
-
Must-have: 8+ years of NAND design-relevant experience with proven knowledge of NAND Flash read, program and erase algorithms.
-
Must-have: Proficiency in analog/mixed-signal circuit design and layout (page buffers, decoders, bias tables and waveforms, PDNs, level shifters, charge pumps, op amps, DACs/ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL/Verilog).
-
Must-have: Strong fundamentals in semiconductor and device physics and understanding of reliability issues (CHC, NBTI, stress, snapback, electromigration, IR analysis).
-
Must-have: Experience with circuit verification and optimization: layout planning, parasitic extraction, block/subsystem/full-chip simulation, corner management, PVT/mismatch analysis, and results qualification.
-
Must-have: Experience with analog/digital simulators such as HSPICE, FastSPICE, and Verilog.
-
Must-have: Proficient Python skills for engineering automation and experience integrating scripts/libraries with EDA tools for simulation control, data extraction, regression management, or reporting.
-
Must-have: Experience with Cadence design tools, LVS/DRC flows and UNIX environments.
-
Nice-to-have: Experience productizing AI/LLM-assisted design flows and prior work on agentic enablement for engineering workflows.
Education Requirements
MS in Electrical Engineering required; PhD preferred. Field: electrical engineering or closely related technical discipline.
About the Company
Company: Micron Technology
Headquarters: Boise, Idaho, USA
Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.

Date Posted: 2026-07-27