Principal CPU Physical Design Engineer

Job Title

Principal CPU Physical Design Engineer

Role Summary

Lead physical implementation of high-performance CPU cores at advanced process nodes, driving timing, power, area (PPA) and manufacturability from RTL to GDS. Work within the CPU engineering team to co-optimize architecture, RTL, circuit design, and physical implementation for production silicon.

Experience Level

Senior — Principal-level role. Expectation of extensive experience (senior technical leadership; typical candidates have 10+ years in ASIC/SoC physical design).

Responsibilities

Primary responsibilities include ownership of physical implementation and improving design quality and scalability.

• Own RTL-to-GDS implementation for critical CPU subsystems, driving PPA convergence and signoff quality.
• Drive timing closure, power optimization, congestion reduction, and area trade-offs for high-frequency CPU blocks.
• Partner with Architecture, RTL, and Circuit teams to co-optimize designs for physical implementation.
• Analyze and resolve silicon issues including variability, EM/IR, power integrity, and manufacturability.
• Develop and deploy flows, methodologies, and automation to improve scalability and QoR across projects.
• Collaborate with EDA vendors and CAD teams to extend tool capabilities and performance.
• Contribute to next-generation physical design strategies for advanced process nodes.
• Mentor and raise the technical level of junior engineers.

Requirements

Must-have technical skills and experience; preferred skills are listed separately.

• Must-have: 10+ years in ASIC/SoC physical design with hands-on RTL-to-GDSII implementation (synthesis, place & route, STA, signoff).
• Must-have: Demonstrated experience in timing closure, power optimization, and PPA trade-offs for high-performance designs.
• Must-have: Scripting proficiency (TCL, Python, or similar) for flow automation and debug.
• Must-have: Practical experience addressing congestion, variability, EM/IR, and power integrity issues.
• Nice-to-have: Prior work on CPU cores or other high-performance microarchitectures.
• Nice-to-have: Experience at advanced nodes (7nm, 5nm, 3nm or below) and strong familiarity with industry-standard tools (Synopsys/Cadence).
• Nice-to-have: Experience developing physical design methodologies and data-driven debug/analysis skills.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field plus 8+ years of relevant engineering experience; OR Master's degree in those fields plus 7+ years; OR PhD in those fields plus 6+ years. Equivalent related work experience is accepted as described in the minimum qualifications.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.