Principal COE Digital Design Engineer

Job Title

Principal COE Digital Design Engineer

Role Summary

Member of the Center of Excellence (COE) within Marvell's Custom Cloud Solutions business unit. Responsible for defining micro-architecture, implementing RTL, and delivering production-ready PCIe/CXL IP subsystems for data center and cloud SoCs.

Work spans architecture, RTL design, verification, physical integration, and post-silicon validation to enable reusable, high-quality IP for internal SoC teams and customers.

Experience Level

Senior — typically 8–10+ years of relevant RTL design experience focused on subsystem-level work (PCIe/CXL preferred).

Responsibilities

Key responsibilities include driving PCIe/CXL subsystem design from architecture through silicon and providing technical leadership across cross-functional teams.

• Define micro-architecture and deliver RTL implementation and integration for PCIe/CXL subsystems.
• Translate architecture and product requirements into robust RTL designs.
• Collaborate with design verification teams on test plans, debug, and coverage closure.
• Partner with Physical Design and DFT teams to ensure RTL is PD-friendly and DFT-ready.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Drive coding best practices, design quality improvements, and reuse across projects.
• Participate in design reviews, milestone reviews, and cross-functional technical discussions.
• Mentor and provide technical guidance to junior designers within the PCIe/CXL domain.

Requirements

Must-have technical skills and experience required to be effective in this role.

• 8–10+ years of RTL design experience, with a track record delivering complex PCIe/CXL controllers or subsystems.
• Strong hands-on SystemVerilog / Verilog RTL development skills.
• Familiarity with PCIe and CXL specifications and implementation details.
• Deep experience with ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Solid understanding of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
• Experience supporting lint, CDC/RDC analysis, synthesis, and design sign-off flows.
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor/Siemens).
• Proficient in scripting (TCL, Perl, Python) and version control systems (GIT, SVN).

Preferred:

• End-to-end PCIe/CXL subsystem RTL execution and sign-off experience.
• Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms.
• Prior experience mentoring engineers and providing cross-functional technical leadership.
• Familiarity with post-silicon bring-up and debug methodologies.

Education Requirements

Master's or Bachelor's degree in Electronics / Electrical Engineering (MS or BS in EE/Electronics). No other degree or certification requirements specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.