Principal Chip Lead, Silicon Co-Design Group

Job Title

Principal Chip Lead, Silicon Co-Design Group

Role Summary

Technical lead responsible for the end-to-end technical integrity of a major silicon program within the Silicon Co-Design Group. Partner with architecture, design, validation, software, and manufacturing to integrate features, resolve multi-functional issues, and maintain qualification methodology.

Experience Level

Senior — 15+ years of experience in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company.

Responsibilities

Accountable for the program's technical direction and cross-functional execution. Typical duties include:

• Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
• Co-lead program-level feature integration from chip to system, identify inter-function dependencies, and drive resolution.
• Resolve the program's hardest multi-team bugs by translating ambiguous symptoms into root-cause closure (areas such as HBM, power & thermal, high-speed I/O, packaging).
• Steward and adapt the qualification playbook; define mitigations and capture reusable methodology.
• Shape the program technical narrative by surfacing risks, trade-offs, and decision-ready options for executive leadership.
• Mentor Chip Leads on adjacent programs and contribute SCG-wide methodology via post-mortems and write-ups.
• Lead Critical Debug and Technical Execution forums and represent the chip externally on technical risks.

Requirements

Must-have qualifications and skills:

• 15+ years of industry experience with a proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company and experience on multiple shipped silicon products.
• Strong end-to-end understanding of SoC and ASIC architecture and recognized expertise in at least one subsystem (for example: HBM, SerDes, power & thermal, or packaging).
• Demonstrated silicon-level impact (faster bring-up, fewer escapes, yield recovery, or methodology contributions), including converting ambiguous multi-team failure modes into root-cause closure and reusable workarounds.
• Proven ability to guide technical decisions across functional boundaries without direct authority and to present complex issues as clear options to executive audiences.

Nice-to-have:

• Prior Chip Lead, Project Tech Lead, Principal or Distinguished Engineer experience on flagship GPUs, AI accelerators, CPUs, networking ASICs, or other large SoCs; patents, papers, or invited talks related to silicon validation or post-silicon debug.
• History of building and sharing reusable methodology (playbooks, debug frameworks, standards) adopted across teams; hands-on debug experience with HBM, high-speed I/O, power & thermal, or packaging.
• Comfort working with globally distributed teams and experience using AI tools to improve team velocity.

Education Requirements

BS or MS in Electrical or Computer Engineering, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.