Principal CAD Engineer Digital Verification

Job Title

Principal CAD Engineer 6 Digital Verification

Role Summary

Provide and maintain scalable verification infrastructure, EDA automation, and methodology enablement to support ASIC/SoC digital verification teams. Collaborate with verification, RTL design, and EDA vendors to improve regression stability, debug efficiency, and time-to-tapeout.

Experience Level

Senior 6 minimum 12+ years of experience in digital verification, CAD, or engineering support roles.

Responsibilities

Deliver CAD support, develop automation, and maintain verification infrastructure; collaborate across teams to resolve flow and tool issues.

• Act as primary CAD interface for design and verification teams to troubleshoot simulation, regression, coverage, and debug flows.
• Deploy, integrate, and maintain EDA tools, scripts, and verification environments.
• Maintain and optimize regression and CI/CD systems and compute-farm/LSF usage for efficient job execution.
• Work with EDA vendors to track, debug, escalate, evaluate, and roll out tools.
• Analyze DV flow performance and implement improvements to reduce bottlenecks and cycle time.
• Support adoption of verification methodologies (UVM, coverage-driven, formal, emulation) and provide training and documentation.
• Provide scripting and automation to streamline repetitive support workflows.
• Partner with cross-functional teams (DV, RTL, system, IT) to resolve issues impacting verification flows.

Requirements

Core technical and interpersonal requirements. See Education Requirements below for degree expectations.

• Must-have:
  • 12+ years in digital verification, CAD, or engineering support roles.
  • Strong understanding of digital verification flows: simulation, regression, coverage, and debug.
  • Hands-on experience with SystemVerilog and UVM (for debugging/support).
  • Proficiency in scripting: Python, Tcl, Perl, or similar.
  • Experience with Linux-based environments.
  • Experience with EDA tools such as VCS, Xcelium, Verdi, vManager.
  • Experience with regression environments, CI/CD systems, and compute-farm management.
  • Basic understanding of SoC/ASIC architecture and RTL design concepts.
  • Strong communication and collaboration skills; experience with globally distributed teams.
• Nice-to-have:
  • Experience with Matlab, Coside, or similar system tools.
  • Familiarity with AI/ML-based DV tools (e.g., Cadence Verisium AI) or AI-assisted verification workflows.
  • Experience with cloud-based or distributed regression environments.
  • Interest in automating support workflows using scripting or AI-based approaches.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.