Principal ASIC Verification Engineer, DDR/LPDDR
SynopsysJob Title
Principal ASIC Verification Engineer, DDR/LPDDR
Role Summary
Lead verification engineering for DesignWare IP with emphasis on DDR/LPDDR and serial interfaces. Manage a verification team, own verification strategy and testbench architecture, and collaborate with RTL designers and architects to deliver production-ready IP.
This role is part of Synopsys' DesignWare IP Verification R&D team based in Bangalore and involves close global collaboration.
Experience Level
Senior - requires 8+ years of hands-on verification experience and proven experience leading verification teams for IP projects.
Responsibilities
Primary responsibilities cover verification planning, implementation, and signoff for IP cores.
- Lead a team of verification engineers through full IP verification cycles, from test plan definition to coverage closure and signoff.
- Design, build, and evolve SystemVerilog/UVM verification environments that scale across product generations.
- Define and review test plans addressing corner cases, protocol compliance, and system-level interactions.
- Write and debug complex testbenches, checkers, and assertions for memory controllers and serial interfaces (including DDR/LPDDR).
- Extract, analyze, and drive functional and code coverage metrics to closure; identify gaps and adjust strategy in real time.
- Collaborate with RTL designers, architects, and circuit teams to align verification scope with design intent.
- Manage regression infrastructure and coordinate with infrastructure teams to keep verification cycles efficient and reliable.
Requirements
Must-have skills and experience; education requirements are listed separately below.
- Proven track record leading verification teams through IP delivery, including planning, execution, and signoff.
- Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow.
- Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs.
- Proficiency in extracting and interpreting functional and code coverage and using those metrics to drive closure.
- Experience verifying serial interface protocols and working within IP design and verification processes.
- Demonstrated ownership of end-to-end verification deliverables, including metric closure and formal review signoff.
- Nice-to-have: hands-on experience with DDR/LPDDR protocols and familiarity with AI-assisted verification tools.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Electronics and Communication Engineering as specified in the posting.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
