Principal ASIC Physical Design Engineer

Job Title

Principal ASIC Physical Design Engineer

Role Summary

Lead end-to-end physical implementation of complex SoCs targeted for high-performance satellite systems, owning the RTL-to-GDSII flow and collaborating with architecture, RTL, DFT, packaging, and test teams.

This role drives physical design methodology, vendor coordination, tool/flow decisions, and first-pass silicon success in advanced FinFET technologies.

Experience Level

Senior — typically requires 10+ years of relevant ASIC physical design experience.

Responsibilities

The core responsibilities include hands-on implementation, technical leadership, and cross-functional coordination.

• Own complete RTL-to-GDSII flow: synthesis, floorplanning, P&R, CTS, STA, and sign-off (DRC/LVS).
• Develop and maintain physical design methodologies, automation, and scripts to optimize performance, power, and area (PPA).
• Drive timing closure across corners and supply domains; perform IR drop analysis and ECO implementation.
• Coordinate package-aware floorplanning and chip-to-board integration with package, SI/PI, and test teams.
• Manage and guide external physical-design partners and service vendors; ensure milestones and quality standards.
• Work with EDA vendors to debug and optimize tool flows and evaluate new methodologies.
• Support chip bring-up, post-silicon debug, and production support through close collaboration with test teams.
• Mentor engineers and act as a technical leader for the physical design team.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 10+ years of ASIC physical design experience for high-performance SoCs.
• Proven end-to-end expertise with industry tool flows (Synopsys, Cadence, Siemens) for physical implementation.
• Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, hierarchical SoCs.
• Experience with advanced FinFET process nodes and foundry sign-off flows.
• Prior experience managing or coordinating outsourced/offshore PD teams or vendors.
• Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
• Excellent communication, leadership, and cross-functional collaboration skills.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated). No other degrees or certifications were specified.

Preferred Qualifications

Nice-to-have experience that will strengthen a candidate's fit.

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Experience driving tapeouts through TSMC or familiarity with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Compensation & Benefits

Base salary range: $190,000 – $280,000 plus equity. Comprehensive benefits including paid time off, medical/dental/vision coverage, life insurance, and paid parental leave.

Location & Compliance

Onsite role. The position requires access to information controlled by U.S. export regulations; applicants must be U.S. Persons or otherwise eligible for required export licenses.

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.