Principal ASIC Package Design Engineer

Job Title

Principal ASIC Package Design Engineer

Role Summary

Lead ASIC package architecture and execution for high-performance, power-dense SoCs with a focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. Own end-to-end package strategy from early architecture and trade studies through vendor qualification and production ramp.

This role is the technical authority on package design, defining standards, influencing silicon and system interfaces, and ensuring first-pass success for complex, high-speed ASICs.

Experience Level

Senior (Principal). Typically requires 10+ years of relevant ASIC package design experience.

Responsibilities

The engineer will define and execute package architectures and lead cross-functional tradeoffs for manufacturable, high-performance ASIC packages.

• Own package architecture for FC-BGA and MCM solutions: substrate stack-up, ball-map strategy, PDN, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, PI/SI, thermal, manufacturability, and reliability.
• Define long-term packaging roadmap for future process nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed FC-BGA design for high-pin-count ASICs with high-speed SerDes and dense power grids.
• Specify substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Lead package-level SI/PI and EM simulation strategy and oversee PDN and decoupling approaches.
• Define thermal architecture at the package level, including lids, TIMs, heat spreaders, and mechanical cooling interfaces.
• Manage relationships with OSATs and substrate suppliers: vendor qualification, capability assessment, and production ramp coordination.

Requirements

Core technical skills and proven delivery experience required for immediate ownership of complex ASIC package programs.

• 10+ years of ASIC package design experience with deep expertise in FC-BGA and delivery of high-pin-count packages into production.
• Proven track record working directly with OSATs and substrate vendors through qualification and volume ramp.
• Strong SI/PI fundamentals at the package level; experience with SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience with substrate technologies, materials selection, and assembly/process optimization.
• Demonstrated thermal management experience for power-dense ASICs at the package level.
• Experience defining PDN, decoupling strategy, and high-speed digital interface (SerDes, JESD, Interlaken) considerations at the package level.
• Experience leading cross-functional trade studies and defining packaging requirements that align with silicon and system constraints.

Nice-to-have:

• Experience with MCM, heterogeneous integration (chiplets, interposers), or advanced laminates.
• Background in aerospace/space or high-reliability electronics and familiarity with qualification/test methodologies used in those industries.
• Experience building or scaling package design methodology and organizational standards.

Education Requirements

Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field (explicitly stated). No advanced degree requirement specified.

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.