Principal ASIC Package Design Engineer

Job Title

Principal ASIC Package Design Engineer

Role Summary

Lead the architecture and execution of advanced ASIC package solutions with primary focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) approaches. Own end-to-end package strategy from early architecture and trade studies through vendor qualification and production ramp.

Serve as the technical authority for package design, defining standards and collaborating with silicon, RF, and systems teams to ensure first-pass success for high-speed, power-dense ASICs.

Experience Level

Senior — requires substantial experience; the role specifies 10+ years of ASIC package design experience.

Responsibilities

Primary responsibilities include leading package architecture, trade studies, and vendor engagement for high-performance ASICs.

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, PDN, signal breakout, and mechanical constraints.
• Lead package-level trade studies covering cost, performance, PI/SI, thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with process nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed FC-BGA design for high-pin-count ASICs with high-speed SerDes and dense power grids.
• Specify substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Co-optimize die floorplans and package interfaces with silicon, RF, and systems teams.
• Own package-level SI/PI strategy and EM simulation activities; coordinate decoupling and PDN design.
• Lead package thermal architecture, including lid/TIM/heat spreader selection and mechanical cooling interfaces.
• Serve as primary technical interface to substrate vendors, OSATs, and assembly houses; drive material and process choices.

Requirements

Must-have technical skills and experience for immediate impact. Education details are listed separately under Education Requirements.

• 10+ years of ASIC package design experience with deep expertise in FC-BGA and delivering production designs.
• Proven track record delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies, materials, and package-level thermal management.
• Expertise in SI/PI and EM simulation tools (examples: SIWave, HFSS, ADS) and applying them to package-level problems.
• Experience working directly with OSATs and substrate vendors and familiarity with qualification and test methodologies.

Nice-to-have

• Experience with MCM, heterogeneous integration, chiplets, or interposers.
• Background in high-speed digital or mixed-signal SoCs and aerospace/high-reliability electronics.
• Experience defining packaging strategy from early architecture through first silicon and volume ramp.
• History of building or scaling package design methodology within an organization.

Education Requirements

Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related technical field is specified.

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.