Principal ASIC DFT Design Engineer - Terawave

Job Title

Principal ASIC DFT Design Engineer - Terawave

Role Summary

Lead design-for-test (DFT) architecture and test strategy for the TeraWave System-on-Chip (SoC) program. This senior individual contributor role owns DFT specification, implementation, and silicon bring-up activities across large multi-block digital SoCs.

The role spans specification through ATE pattern debug, production test vector delivery, and support for defect and yield analysis to ensure manufacturability and test quality.

Experience Level

Senior - minimum 10 years of experience in DFT for complex digital SoCs as stated in the posting.

Responsibilities

Accountable for DFT architecture, specification, implementation, and silicon test readiness. Key responsibilities include:

• Define DFT architecture and test strategy for large multi-block SoC designs.
• Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms.
• Implement scan chain insertion, test clock control, and on-chip compression logic.
• Design memory and logic built-in self-test (BIST) infrastructure for embedded memories and logic.
• Generate and validate DFT vectors for silicon bring-up and production test programs.
• Debug ATE pattern failures and drive resolution with design and product engineering teams.
• Support defect analysis and yield improvement using test coverage and silicon failure data.
• Review test coverage and DFT timing metrics with physical design and verification teams.

Requirements

Must-have technical skills and experience; preferred items listed where noted.

• Minimum 10 years' experience in DFT for complex digital SoCs (must-have).
• Proven experience defining DFT architecture and writing DFT specifications for large multi-block SoCs (must-have).
• Hands-on experience with DC and AC scan design, and memory BIST implementation (must-have).
• Experience generating ATPG patterns for automated test equipment (ATE) and debugging ATE patterns (must-have).
• Experience with hierarchical DFT, test access standards (IEEE 1500 / IEEE 1687) and commercial DFT tool flows (e.g., Tessent, DFTMAX, Modus) (preferred).
• Experience with defect analysis, yield improvement for advanced process-node silicon, and test time/cost reduction techniques (preferred).
• Strong written and verbal communication skills for presenting test strategy to technical stakeholders (preferred).

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required. A Master’s degree in Electrical Engineering, Computer Engineering, or related technical field is preferred. Equivalent practical experience may be acceptable where explicitly stated by the employer.

Additional Notes

Applicants must be legally authorized to work in the United States; Blue Origin specifies applicants must be a U.S. citizen or national, U.S. permanent resident (Green Card holder), or lawfully admitted as a refugee or granted asylum. This role has no direct reports and requires engagement with cross-functional engineering teams during silicon bring-up and production test phases.

Blue Origin states base pay ranges for certain US locations; ranges may vary by site and local law.

Equal Opportunity

Blue Origin is an Equal Opportunity/Affirmative Action employer and provides reasonable accommodation requests via a publicly managed inbox for EEO and accommodation inquiries.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.