Principal ASIC Design Verification Engineer

Job Title

Principal ASIC Design Verification Engineer

Role Summary

Lead verification engineer responsible for defining and executing verification strategies for custom ASIC/SoC designs, from block level through full-chip and post-silicon validation. Works closely with architecture, RTL, DFT, firmware, physical design, and silicon validation teams.

K2 Space designs high-power satellite systems; this role offers hands-on ownership of first-generation silicon in a fast-paced hardware development environment.

Experience Level

Senior — requires extensive experience; the posting specifies 10+ years of ASIC/SoC verification experience.

Responsibilities

Key responsibilities include planning and executing verification activities and driving improvements to verification practice.

• Develop and execute verification plans for block, subsystem, and full-chip levels.
• Build SystemVerilog/UVM testbenches: agents, monitors, scoreboards, checkers, and coverage models.
• Author SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Design constrained-random and directed tests to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, perform root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional, code, and assertion coverage; drive coverage closure for sign-off.
• Manage regression suites, simulation farms, and CI pipelines for high throughput and fast debug cycles.
• Participate in design reviews and microarchitecture discussions; influence design-for-verification practices.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug.
• Lead large or complex verification efforts and manage external IP/verification partners as needed.
• Participate in ASIC team interviewing and mentoring activities.

Requirements

Must-have technical skills and experience. "Nice-to-have" items are listed separately.

• 10+ years of ASIC/SoC verification experience (senior-level contributor).
• Deep knowledge of SystemVerilog, digital logic, RTL design and verification flows.
• Proven experience with UVM-based testbench development, constrained-random testing, functional coverage, and assertions.
• Familiarity with major simulators and debug tools (examples: VCS, Xcelium, Questa; Verdi/SimVision) and coverage tools.
• Proficiency with scripting for automation and debug (examples: Python, Perl, TCL) and revision control (Git).
• Experience with regression management, CI/CD automation, and gate-level simulation.
• Experience integrating reference models and working with embedded processor-based designs and firmware (C/C++).
• Familiarity with industry-standard interfaces (examples: APB/AHB/AXI) and DFT/scan methodologies.
• Involvement in post-silicon validation planning and execution.
• Must be eligible as a U.S. person per export control requirements (see 22 C.F.R. § 120.15).

Nice-to-have:

• Low-power verification experience and analog behavioral modeling.
• Familiarity with physical design flows and RF/digital mixed systems.
• Experience working in distributed, cross-functional teams and in space or telecom domains.

Education Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.