Principal ASIC Design Engineer (Starshield)

Job Title

Principal ASIC Design Engineer (Starshield)

Role Summary

Join the Starshield team to design next-generation ASICs and FPGAs for space and ground systems that support U.S. national security programs. Work closely with modem/DSP, RFIC, verification, and physical implementation teams to take designs from architecture through silicon bring-up.

Experience Level

Senior — 8+ years of relevant experience in RTL implementation and/or FPGA/ASIC development.

Responsibilities

Primary responsibilities include architecture, RTL implementation, verification support, and silicon validation.

• Design digital ASICs and FPGAs for Starshield programs.
• Evaluate architectural trade-offs and derive subsystem specifications; partition functions between hardware and software.
• Define micro-architecture and implement RTL in Verilog/SystemVerilog; integrate at top level and deliver synthesis-/timing-clean designs.
• Collaborate with verification teams to ensure comprehensive coverage and verification of designs.
• Provide timing constraints for IP, support synthesis, timing closure, and perform formality checks.
• Participate in silicon bring-up and validation; assist development of automated test lab equipment for measurements.

Requirements

Must-have qualifications and relevant skills; preferred items noted.

• Must-have: 8+ years of experience in RTL implementation and/or FPGA/ASIC development.
• Must-have: Strong RTL design skills in Verilog/SystemVerilog and experience delivering synthesis- and timing-clean designs.
• Experience with static timing analysis, timing constraints, synthesis flows, and closure processes.
• Familiarity with EDA tools and flows, e.g. HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA tools (Xilinx Vivado, Intel/Altera Quartus).
• Ability to work effectively with verification, physical design, modem/DSP, and RF teams.
• ITAR eligibility required: must be a U.S. person (U.S. citizen, U.S. national, lawful permanent resident, refugee, or asylee) or be eligible to obtain required Department of State authorizations.
• Ability to work long hours and weekends when necessary; willingness to travel for off-site testing.
• Preferred: experience with clock domain crossing solutions, power optimization, complex ASIC development, multicore CPU subsystems, standard bus protocols (AXI/AHB), embedded processors, high-speed/low-power design techniques, and scripting (Python, TCL).
• Preferred: prior experience on classified programs or active security clearance (TS-SCI may be advantageous).

Education Requirements

Bachelor's degree in electrical engineering, computer engineering, or computer science is required.

Compensation: Base pay range $200,000 - $285,000 per year; candidates with an active clearance may receive a differential (approximately 10%, up to an additional $20,000 annually). Additional benefits and long-term incentives may apply.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.