Director - R&D Technical Head

Job Title

Director - R&D Technical Head

Role Summary

Lead Semtech's India R&D engineering organization for end-to-end chip design and silicon delivery across SoC, analog, digital, verification, DFT, packaging and test. Own technical strategy, architecture decisions, toolchain adoption, cross-vertical coordination and tapeout readiness to meet PPA and first-silicon targets.

Manage and mentor engineering leaders, align projects with foundry and IP partners, and serve as principal technical escalation for complex design issues.

Experience Level

Senior-level; typically requires 20+ years in the semiconductor/VLSI industry with at least 5 years in senior engineering leadership or technical management.

Responsibilities

Primary responsibilities include technical strategy, people leadership, project oversight, and stakeholder reporting.

• Define and own chip design strategy, methodology and technology roadmap across SoC, analog, digital, verification, DFT, packaging and test.
• Set design standards and quality benchmarks to achieve PPA targets and first-silicon success.
• Evaluate and adopt EDA toolchains and modern design methodologies.
• Provide architectural guidance on SoC partitioning, IP integration, mixed-signal co-design and DFM.
• Directly manage vertical leads and engineering managers; set goals and development plans for a 12–20+ engineer organization.
• Drive talent acquisition and define technical interview frameworks for senior hires.
• Monitor projects from architecture through tapeout; run design reviews and tapeout readiness and lead silicon bring-up planning.
• Act as primary technical escalation point; lead root-cause analysis across domains.
• Prepare R&D status reports, technical risk assessments and resource utilization dashboards for senior leadership.
• Engage with foundry partners and IP vendors to optimize design flows and process qualifications.

Requirements

Must-have skills and experience.

• 20+ years of progressive semiconductor/VLSI experience with demonstrable chip design delivery to GDS tapeout.
• Minimum 5 years in senior engineering leadership or technical management overseeing multiple projects and teams.
• Hands-on expertise across chip design flow: SoC architecture, physical design, analog, digital RTL, verification, DFT, packaging and test engineering.
• Deep proficiency with industry EDA tools (Cadence, Synopsys; e.g., Innovus, Virtuoso, Design Compiler, IC Compiler, PrimeTime).
• Proven track record managing concurrent chip projects and resolving technical blockers to meet milestones.
• Strong written and verbal English communication; ability to present complex technical concepts to executives.

Nice-to-have:

• Experience leading geographically distributed R&D teams of 25+ engineers.
• Exposure to advanced packaging (2.5D/3D), chiplets, AI/ML-assisted EDA flows, automotive-grade/high-reliability products.
• Experience working with foundries (TSMC, GlobalFoundries) on advanced node qualifications and PDK evaluation.
• Publication record or patents in semiconductor design or device physics.
• Experience with HR processes: headcount planning, compensation benchmarking, performance management.

Education Requirements

Bachelor's degree (B.E. / B.Tech) in Electronics & Communication Engineering, Electrical Engineering, VLSI Design or a closely related field required; Master’s degree (M.E. / M.Tech / M.S.) strongly preferred.

About the Company

Company: Semtech

Headquarters: Camarillo, California, USA

Semtech Corporation is a high-performance semiconductor company providing IoT systems and Cloud connectivity solutions. The company focuses on delivering innovative technology solutions that support a smarter, more connected, and sustainable planet, with a dedication to quality across infrastructure, industrial, and consumer markets.