Principal ASIC Design Engineer - Memory Interface IP (HBM/DDR/LPDDR)
SynopsysJob Title
Principal ASIC Design Engineer - Memory Interface IP (HBM/DDR/LPDDR)
Role Summary
Lead design and delivery of high-performance memory interface IP (HBM, DDR, LPDDR) from architecture through RTL implementation and verification handoff. Work across digital, analog, physical design, verification, and customer integration teams to ensure production-quality IP and successful silicon bring-up.
Experience Level
Senior level - typically 8–10+ years of hands-on ASIC digital design experience, with substantial RTL and production IP delivery background.
Responsibilities
Primary technical and leadership responsibilities for memory interface IP development and customer integration.
- Design and own complex RTL blocks for HBM, DDR, and LPDDR memory interfaces from architecture to implementation handoff.
- Collaborate with analog and physical design teams to validate mixed‑signal interfaces and achieve timing closure and signal integrity.
- Develop and execute detailed verification plans, including corner-case analysis and protocol compliance testing.
- Drive timing, power, and area optimization using industry EDA tools (e.g., Synopsys Fusion Compiler, PrimeTime, DC Compiler).
- Lead technical reviews and design audits; assess architecture tradeoffs and implementation risks.
- Mentor and review work of other engineers to raise RTL quality and design judgment.
- Work directly with customer engineering teams to debug integration issues and support IP deployment in customer SoCs.
Requirements
Essential technical skills and experience required to perform the role.
- 8–10+ years of hands-on ASIC digital design experience focused on RTL design and verification.
- Deep expertise in at least two memory protocols: HBM, DDR4, DDR5, LPDDR4, LPDDR5.
- Proven track record of designing and delivering production-quality IP or SoC blocks that taped out and were validated in silicon.
- Strong SystemVerilog RTL skills and familiarity with UVM or equivalent verification methodologies.
- Experience integrating AMBA protocols (AXI, AHB, APB) within memory subsystems.
- Proficiency with Synopsys or Cadence EDA toolchains for synthesis, timing analysis, and power optimization.
- Excellent debugging skills for timing, protocol, and integration issues; effective cross-functional communication with analog and customer teams.
- Nice-to-have: direct experience with mixed‑signal interface design and collaboration with analog teams.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
