Principal ASIC Design Engineer

Job Title

Principal ASIC Design Engineer

Role Summary

Lead architect and implementer of complex RTL modules and subsystems for high-performance networking ASICs. Work on specification, micro-architecture, RTL implementation, power- and timing-aware design, and cross-functional validation to deliver production-quality silicon.

Role reports into ASIC/SoC engineering and provides technical leadership, design ownership, and mentorship to junior engineers and interns.

Experience Level

Senior level — expects an experienced engineer with substantial track record; the posting specifies 15+ years of relevant ASIC design experience.

Responsibilities

Primary responsibilities include end-to-end design and delivery of RTL blocks and subsystems.

• Architect complex modules and subsystems for high-performance networking chips.
• Create detailed functional and micro-architecture specifications that meet power, area, and performance targets.
• Implement RTL using Verilog/SystemVerilog and drive design to final netlist.
• Develop functional coverage and SVA assertions to exercise corner cases in verification.
• Apply power-reduction techniques during architecture and implementation phases to meet power targets.
• Work with physical design for timing closure and perform RTL fixes to meet frequency goals.
• Collaborate with verification teams to validate blocks and resolve issues uncovered in verification.
• Provide technical leadership and mentor new graduates, junior engineers, and interns.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Extensive experience (senior-level) in RTL architecture, design, and implementation of high-performance ASIC subsystems.
• Strong RTL coding skills in Verilog and SystemVerilog.
• Experience authoring functional coverage and SystemVerilog assertions (SVA) for verification.
• Practical knowledge of synthesis, lint, timing closure flows, and tools used in typical ASIC development.
• Experience applying power reduction techniques in architecture and RTL implementation.
• Proven ability to lead design from specification through to final netlist and interact cross-functionally.
• Strong analytical, problem-solving, written, and verbal communication skills.
• Leadership and mentorship experience guiding junior engineers and interns.
• Nice-to-have: familiarity with computer architecture and networking protocols; scripting in Perl or Python.

Education Requirements

Bachelor's degree in Electrical Engineering required; Master’s degree strongly desired. The posting specifies 15+ years of relevant ASIC design experience.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.