Principal ASIC Design Engineer

Job Title

Principal ASIC Design Engineer

Role Summary

As Principal ASIC Design Engineer in Central Engineering, you will lead front-end design methodologies and flows that bridge RTL and physical implementation across multiple SoC product lines. You will enable early detection of physical and timing issues and ensure robust handoff to back-end teams.

This is a hands-on technical leadership role focused on synthesis, static timing analysis, CDC/RDC, constraints, and automation to deliver timing-critical, production-quality silicon.

Experience Level

Senior — typically 8–20 years of relevant industry experience (employer guidance: 8+ years with a Master’s/PhD; 10+ years with a Bachelor’s).

Responsibilities

Lead and execute front-end methodologies and collaborate with cross-functional teams to deliver timing-critical SoC designs.

• Define and implement front-end methodologies for synthesis, static timing analysis, and clock/reset domain crossing (CDC/RDC).
• Develop flows that enable early detection of physical design and timing challenges and ensure efficient handoff to back-end teams.
• Provide high-quality timing and implementation constraints aligned with architecture and design intent.
• Drive timing closure and power optimization across the front-end design flow.
• Collaborate with Architecture, RTL Design, Physical Design, Timing, and DFT teams throughout the SoC lifecycle.
• Create and maintain automation and tooling (e.g., Python/Perl) to improve design productivity and repeatability.

Requirements

Core technical and practical qualifications required to perform successfully in this role.

• Must-have: Strong foundation in ASIC design, verification, architecture, and front-end design methodologies.
• Must-have: Proficiency in Verilog/SystemVerilog, linting, synthesis, static timing analysis, CDC/RDC, and formal equivalence checking.
• Must-have: Solid understanding of back-end design, EDA tools, and timing-driven implementation strategies.
• Must-have: Hands-on experience with SoC architecture including processor cores, memory subsystems, and peripheral interfaces.
• Must-have: Scripting and automation skills (Python or Perl) and a demonstrated track record of delivering production-quality silicon on aggressive timelines.
• Nice-to-have: Experience with high-speed protocols (Ethernet, PCIe, emerging standards), high-speed datapath design, large datapath FPGAs, or advanced process nodes.
• Nice-to-have: Familiarity with applying AI/ML techniques to ASIC development.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field (with approximately 10–20 years of industry experience); or a Master’s or PhD in a related field (with approximately 8–20 years of experience). No specific certifications listed; equivalent-experience language not specified in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.