Principal Applications Engineer, Prime Power RTL

Job Title

Principal Applications Engineer, Prime Power RTL

Role Summary

The Principal Applications Engineer is a technical authority for RTL-stage power analysis within the low-power design portfolio. This role leads strategic customer engagements, develops end-to-end methodologies, and coordinates cross-functional teams to drive adoption of RTL power flows for complex SoC, AI accelerator, and mobile processor designs.

Experience Level

Senior (Principal) level. See Education Requirements for degree and equivalent experience details.

Responsibilities

Primary responsibilities include strategic customer engagement, methodology architecture, cross-tool integration, and mentoring.

• Act as primary technical advisor for Tier‑1 and strategic accounts on RTL power budgeting, architecture exploration, and pre‑implementation signoff; engage with customer executive leadership.
• Architect end‑to‑end RTL power methodologies (logical CGE/lint/ODC, physical glitch/RTLA, hybrid NDM import, WCDF calibration, FSDB stimulus quality, multi‑rail UPF analysis).
• Lead complex evaluations demonstrating PPRTL correlation with PrimeTime PX and emulation metrics; define flow and calibration strategy in ambiguous customer situations.
• Resolve cross‑tool escalations and production issues; coach and approve work of Staff+ AEs; deliver advanced training and structured R&D feedback.
• Drive multi‑tool deployments spanning PPRTL, VCS, Verdi, PrimeTime, RTL Architect, Fusion Compiler, and UPF/low‑power verification flows.
• Partner with Sales on strategic opportunities: benchmarks, license expansion, and cross‑functional Apps/R&D/Marketing initiatives.

Requirements

Must-have technical skills and professional capabilities; preferred items listed separately.

• Expert knowledge of RTL power: CGE/CGR/DACGE, glitch behavior, memory impact, and multi‑rail UPF domains.
• Hands‑on experience with Prime Power RTL and related tools (VCS, Verdi, SDF, UPF) and strong Tcl-based flow development skills.
• Proven track record leading complex customer engagements with measurable business impact and the ability to engage at executive levels.
• Experience resolving cross‑tool escalations and providing actionable feedback to R&D and product teams.
• Ability to design and validate correlation strategies between RTL power analysis and signoff flows.
• Nice-to-have: PrimeTime PX signoff correlation experience; RTL Architect, Fusion Compiler, NDM flows; ZeBu/emulation-based power analysis; VC SpyGlass/VC LP; IEEE 1801 UPF expertise; publications or presentations (DAC/SNUG); AI, mobile, or datacenter SoC RTL power experience.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required; MS or PhD preferred. Equivalent experience accepted per posting: typical equivalence stated as BS + 10 years related experience or MS + 8 years.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.