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Principal Analog/Mixed-Signal ASIC Engineer

Taara
August 31, 2026
Full-time
Remote friendly (Sunnyvale, California, United States)
Worldwide
$258,000 - $294,000 USD yearly
ASIC Design Jobs, Level - Senior

Job Title

Principal Analog/Mixed-Signal ASIC Engineer

Role Summary

Lead ASIC design, tape-out, and delivery for co-integrated electronic and photonic modules used in long-range free-space optical communication systems. Join a small R&D team developing integrated optical phased array systems and custom mixed-signal ASICs.

Experience Level

Senior β€” principal level. Prefer candidates with 10+ years of relevant industry experience in analog/mixed-signal ASIC design and tape-out ownership.

Responsibilities

The role is responsible for top-level ASIC architecture, hands-on AMS design and layout contributions, and leading tape-out and validation efforts.

  • Own ASIC top-level architecture and delivery for co-integration with photonic integrated circuits.
  • Lead and coordinate a small team of ASIC design and layout engineers through multiple tape-outs.
  • Perform hands-on analog/mixed-signal design and layout work as needed.
  • Drive verification and signoff workflows including DRC, LVS, power integrity, and signal integrity checks.
  • Optimize system-level tradeoffs between ASIC and photonic subsystems and contribute to product strategy.
  • Plan and execute validation of ASIC dies and integration with partner modules.

Requirements

Must-have technical qualifications and experience.

  • 10+ years of industry experience in analog/mixed-signal circuit design and implementation in modern CMOS technologies.
  • Deep design expertise in one or both: high-precision AMS circuits (ADCs/DACs, bandgaps, regulators, amplifiers) and high-speed wireline/silicon-photonics interface circuits (modulator drivers, TIAs, broadband serial links).
  • Proven experience owning top-level ASIC architecture and coordinating engineering teams through tape-out lifecycle.
  • Hands-on experience leading multiple ASIC tape-outs at commercial foundries.
  • Practical experience with DRC, LVS, power integrity (PI), and signal integrity (SI) verification flows.
  • Nice-to-have: SoC verification planning, RTL and RTL-to-GDS flows, commercial layout verification tools (Calibre or equivalent), version control (SOS/Git), and experience taking products from prototype to production.

Education Requirements

Ph.D. in Electrical Engineering or a related field.


About the Company

Company: Taara

Headquarters: Sunnyvale, CA, USA

Born at X, Google's Moonshot Factory, Taara develops wireless optical communication systems and photonics chip technologies to deliver high-speed, affordable internet to underserved regions worldwide.

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Date Posted: 2026-08-29