Principal Analog Layout Engineer
Join Marvell's Central Engineering AMS-IP team in San Diego to implement analog/mixed-signal layouts for high-speed SerDes and other AMS IP used across Marvell SoCs. Deliver production-ready layout, drive physical-verification closure, and collaborate with circuit designers and PV teams to support SoC integration.
Senior-level (principal) engineering role. See Education Requirements for degree-specific experience guidance.
Primary technical and cross-functional duties for the role.
Must-have technical skills and professional behaviors.
Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 15+ years of related professional experience; Master's degree in Computer Science, Electrical Engineering, or related field with ~10–12 years of experience; PhD in Computer Science, Electrical Engineering, or related field with ~8–10 years of experience. Fields cited: Computer Science and Electrical Engineering or related technical disciplines.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
