Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)

Job Title

Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)

Role Summary

Join the Interface Pathfinding team to design and validate advanced PHY analog circuits for high-speed chip-to-chip and memory interconnect. The role leads development of custom clocking, transmitter, and receiver analog blocks and owns the project lifecycle from specification through post-silicon characterization.

Experience Level

Senior level — requires significant experience (10+ years) in analog/mixed-signal IC design and multiple tape-outs in primary ownership roles.

Responsibilities

The role focuses on transistor-level analog design, architecture decisions for PHY analog blocks, and hands-on post-silicon validation.

• Lead design of specialized analog components, emphasizing clocking (PLL, DLL, CDR) and transmitter/receiver circuits.
• Drive top-level PHY analog architecture: clocking topology and signal-chain partitioning.
• Develop and maintain transistor-level simulation testbenches; run process-corner, Monte Carlo, and mismatch analyses to evaluate margin and yield sensitivity.
• Define clear interface specifications between custom analog blocks and digital control wrappers.
• Work closely with layout engineers to guide custom analog layout and support post-silicon lab characterization.

Requirements

Key technical requirements and preferred skills. Must-haves are listed first; nice-to-have items follow.

• Must-have: 10+ years of analog/mixed-signal IC build experience with at least one tape-out in a primary circuit ownership role.
• Must-have: Deep expertise in clocking circuit design (PLL, DLL, CDR) and transistor-level implementation in advanced CMOS nodes.
• Must-have: Strong transistor-level simulation skills (HSpice or equivalent); experience with corner, Monte Carlo, and mismatch analysis for yield-aware development.
• Must-have: Proven understanding of jitter analysis and its impact on high-speed link timing margins.
• Must-have: Comfortable applying AI/ML/LLM tools to improve productivity and analysis.
• Nice-to-have: Experience with high-speed transmitter architectures (pre-emphasis, swing control, impedance matching) and multi-Gbps die-to-die or SerDes interfaces.
• Nice-to-have: Background in receiver development (sense amps, CTLE/DFE equalization, samplers, calibration).
• Nice-to-have: Familiarity with short-reach PHY standards (UCIe, AIB, BoW) or custom die-to-die PHY architectures.
• Nice-to-have: Experience with OTP/fuse-based calibration and analog trim loop implementation.
• Nice-to-have: Post-silicon characterization experience correlating simulation to measured eye diagrams, BER, phase noise, and jitter histograms.

Education Requirements

BS, MS, or PhD in Electrical Engineering or a related technical field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.