Principal Analog and Mixed-Signal Engineer

Job Title

Principal Analog and Mixed-Signal Engineer

Role Summary

Lead transistor-level analog and mixed-signal design for high-speed memory and interconnect PHY IP (DDR/LPDDR, HBM, UCIe, mobile storage) on advanced FinFET nodes. Work across SPICE simulation, layout collaboration, verification, and silicon bring-up within the Solution IP R&D team.

Team: Solution IP R&D — collaborative analog and digital designers building PHY IP. Accommodation contact: hr-help-canada@synopsys.com.

Experience Level

Senior — expects advanced experience: PhD with 6+ years or Master's with 8+ years of analog and mixed-signal IC design experience.

Responsibilities

Primary responsibilities include circuit design, verification, documentation, and collaboration with layout and customer teams.

• Define analog and mixed-signal sub-block specifications from JEDEC and other standards for DDR/LPDDR, HBM, UCIe, and mobile storage PHY IP.
• Design transistor-level circuits including equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgap references, ADCs, and DACs.
• Develop verification strategies using SPICE simulators and Verilog-A models to ensure coverage across PVT corners.
• Collaborate with layout engineers to minimize parasitics, manage device stress, and implement ESD protection.
• Document circuit designs, test plans, and reliability considerations for tape-out.
• Support electrical characterization and silicon bring-up; present simulation data and design tradeoffs to internal teams and customers.

Requirements

Must-have technical skills and experience.

• Deep expertise in transistor-level CMOS design with strong fundamentals in device physics and matching.
• Proven experience designing circuits in FinFET process technologies.
• Detailed design experience with high-speed sub-circuits (equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgaps, ADCs/DACs).
• Working knowledge of ESD protection techniques and layout strategies to minimize parasitics and device stress.
• Proficiency with schematic entry and SPICE simulation tools (e.g., Spectre, HSPICE) and experience using Verilog-A models for verification.
• Strong understanding of design-for-reliability considerations: electromigration, IR drop, aging, and layout-dependent effects.
• Clear technical communication and documentation skills for both internal stakeholders and customers.
• Nice-to-have: scripting in Python, Perl, TCL, MATLAB, or C to automate simulation flows and custom analysis tools.

Education Requirements

PhD with 6+ years or Master's with 8+ years of analog and mixed-signal IC design experience (as stated in the source). No additional degree fields or certifications were specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.