Principal AMS Layout Engineer

Job Title

Principal AMS Layout Engineer

Role Summary

Lead engineer on the High-Speed Mixed-Signal IP Layout Team responsible for defining and executing layout methodology and delivery for high-speed SerDes and analog/mixed-signal IP. The role combines hands-on layout work, debugging, workflow and methodology development, customer interfacing, and mentoring.

Experience Level

Senior (Principal level). The position expects extensive experience in high-speed analog/mixed-signal layout and leadership; no specific years of experience are stated.

Responsibilities

Key responsibilities include:

• Define and manage layout scope, effort, schedules, deliverables, and customer-specific requirements.
• Accelerate layout development for high-speed SerDes IP to meet quality, schedule, and budget objectives.
• Serve as the primary technical interface for customers and internal teams; present project status, risks, and mitigation plans.
• Gather customer requirements and translate them into technical specifications and workflow improvements.
• Perform hands-on debugging and root-cause analysis of complex layout issues.
• Collaborate on layout approaches that consider advanced packaging (2.5D/3D, interposers, bump strategy) where applicable.
• Develop, validate, and refine end-to-end layout workflows that improve quality, consistency, and efficiency; maintain related documentation.
• Innovate analog/mixed-signal layout methodologies and drive automation using industry-standard tools.
• Ensure signoff quality across DRC/LVS, EM/IR, reliability, parasitics, and tapeout readiness.
• Mentor junior engineers, promote best practices, and foster cross-team knowledge sharing.

Requirements

Must-have and preferred technical qualifications:

• Must-have: In-depth familiarity with high-speed SerDes and analog/mixed-signal layout; strong hands-on debugging and problem-isolation skills; proficiency with Synopsys Custom Compiler or equivalent custom layout tools; experience with verification tools such as ICV, Star-RCXT, PERC or equivalents; knowledge of reliability-driven layout (EM/IR) and parasitic-aware layout practices; experience with custom digital layout and ESD/latch-up mitigation; experience using Jira/Atlassian or similar tools.
• Strong advantage: Experience with multi-Gbps NRZ and PAM4 SerDes.
• Nice-to-have: Knowledge of advanced packaging (2.5D/3D, interposers, bump strategy); experience porting layouts across nodes and foundries; prior customer-facing or leadership experience.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.