Principal AMS Engineer

Job Title

Principal AMS Engineer

Role Summary

Lead architecture, design, integration, and validation of high-speed analog and mixed-signal (AMS) technologies for next-generation SoCs and interfaces. Work across AMS/PHY architecture, circuit design, SoC integration, package/board co-design, and silicon validation through tapeout and production.

This is a hands-on technical leadership role that requires cross-domain collaboration with digital, verification, physical design, packaging, board, and systems teams to deliver production silicon.

Experience Level

Senior / Principal-level engineering role.

Responsibilities

Core responsibilities include leading AMS architecture and driving cross-domain integration.

• Architect and develop analog and mixed-signal circuits and subsystems for high-speed interfaces and SoCs.
• Lead integration of high-speed PHY technologies (die-to-die, UCIe-class, DDR, HBM, SerDes/PHY functions).
• Design and guide development of clocking, reference, DLL/PLL, voltage monitoring, calibration, and data-path analog IP.
• Drive chip/package/PCB co-design for signal and power integrity.
• Own AMS integration into SoCs: interface definition, floorplanning, clocking, timing/STA, power intent, IO and physical implementation considerations.
• Partner with digital, verification, physical design, package, board, and systems teams to resolve cross-domain issues.
• Define requirements and evaluate internal and third-party analog, PHY, and interface IP; manage external IP/design-service engagements.
• Take designs from pre-silicon architecture through tapeout, bring-up, characterization, post-silicon validation, and production.
• Provide technical leadership, conduct design reviews, mentor engineers, and establish AMS design flows and standards.

Requirements

Must-have technical skills and experience; items listed as desired are nice-to-have.

• Deep experience in analog and mixed-signal IC design and implementation.
• Strong background in high-speed PHY architecture and design (e.g., DDR, HBM, die-to-die, SerDes, MIPI or similar).
• Experience developing and integrating analog IP such as PLLs/DLLs, clocking circuits, voltage/reference circuits, ADC/DACs, LDOs, and IO.
• Strong understanding of SoC integration including clocking, timing/STA, low-power design, UPF, IO integration, floorplanning, and physical design interaction.
• Experience with high-speed signal integrity and power integrity across chip, package, and PCB.
• Proven track record taking complex silicon designs from architecture through tapeout and post-silicon validation.
• Experience collaborating closely with package, board, digital, verification, physical-design, and system engineering teams.
• Strong technical judgment and ability to drive ambiguous, cross-functional engineering problems and influence architecture without formal authority.

Nice-to-have:

• Direct experience with UCIe or proprietary die-to-die interfaces.
• Experience with advanced packaging, chiplets, or multi-die systems.
• Experience developing complete PHY subsystems from architecture through silicon validation.
• Background in IO/ESD and latch-up design and qualification.
• Experience with analog timing characterization and design-flow/CAD infrastructure.
• Experience managing third-party IP and design-service vendors or building new design teams and flows.

Education Requirements

Master’s degree or Ph.D. in Electrical Engineering, Electronics Engineering, Microelectronics, or a related technical field, or equivalent practical experience.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.