Principal Advanced Packaging Design Engineer

Job Title

Principal Advanced Packaging Design Engineer

Role Summary

Lead package architecture and design for advanced multi-chip and multi-component packaging solutions (2.5D/3D, co-packaged copper/optical, advanced substrates) for high-performance computing, AI, and networking products. Work with simulation, thermal-mechanical, and electrical teams to meet signal integrity, power integrity, thermal, mechanical, manufacturability, and reliability targets.

Experience Level

Senior-level. Typical experience guidance provided in Education Requirements (see below): Ph.D. ~8+ years, Master’s ~12+ years, Bachelor’s ~15+ years.

Responsibilities

Deliver packaging solutions and lead small cross-functional teams through architecture, design, simulation, and supplier integration.

• Lead small project teams of design and simulation engineers to deliver package designs and development vehicles.
• Define package architecture and drive technology selection for performance products and thermal-mechanical development vehicles.
• Interface with package suppliers to ensure manufacturability, reliability, performance, and cost targets.
• Drive signal integrity and power integrity trade-offs across substrate, board, package, and system levels.
• Manage cross-functional programs, present technical decisions, and document design rationale and test results.
• Contribute to tool, process, and workflow development and maintain design libraries.

Requirements

Essential technical skills, tools, and experience for the role.

• Extensive experience in substrate and/or board design for advanced packaging technologies (2.5D/3D, advanced substrates).
• Strong understanding of design-for-manufacturing (DFM), reliability principles, and electrical performance trade-offs.
• Proven ability to lead complex package architecture projects with internal and external stakeholders.
• Expertise with industry-standard packaging and SiP tools and workflows such as Cadence 3DIC, ISP, APD, and SiP.
• Hands-on experience with signal and power integrity across package and system levels.
• Experience with memory and high-speed interfaces: HBM, DDR, SerDes, D2D, D2H, PCIe, Ethernet, ADC/DAC.
• Familiarity with EDA and mechanical tools: Cadence Sigrity, Clarity, Innovus, Virtuoso; Ansys; AutoCAD; SolidWorks.
• Experience developing and testing thermal-mechanical development vehicles and reliability-driven designs.
• Strong program management, communication, presentation, and documentation skills; ability to work across global time zones.

Education Requirements

Bachelor's in Electrical Engineering or a related technical field with ~15+ years relevant experience; Master's degree with ~12+ years relevant experience; or Ph.D. with ~8+ years relevant experience. The posting also allows equivalent practical experience in place of degree-specific guidance. Fields referenced: Electrical Engineering or related technical disciplines. No specific certifications were mandated.

Compensation: Expected base pay range (USD): 168,400 - 249,310 per annum. Role is eligible for bonus and equity programs.

Note: This position may require eligibility to access export-controlled technology; applicants may be subject to export license review. For reasonable accommodation during the selection process, contact Marvell HR Helpdesk at TAOps@marvell.com.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.