Power Model Engineer

Job Title

Power Model Engineer

Role Summary

Develop power models and analysis methods to support architecture exploration, RTL correlation, and silicon validation for RISC-V processors.

The role partners with architecture, RTL, implementation and validation teams to predict and optimize power across architecture, logic and circuit levels.

Experience Level

Mid-level (3+ years of relevant experience, see Requirements).

Responsibilities

Primary responsibilities include:

• Develop power models for architecture exploration and design trade-offs.
• Correlate power models with RTL simulations and silicon measurements.
• Predict power impact of design changes and propose mitigation or optimization strategies.
• Collaborate with architects, RTL designers, backend and validation teams to inform power-aware decisions.

Requirements

Must-have:

• 3+ years of experience in power analysis and modeling.
• Experience assessing power impacts at architecture, logic-design, and circuit levels.
• Strong knowledge of high-performance out-of-order CPU architecture.
• Experience with ASIC power analysis and optimization.
• Competency in software engineering best practices for large object-oriented codebases.
• Self-starter with strong problem-solving skills.

Nice-to-have:

• Hands-on expertise in hardware development flows (RTL, implementation, verification, backend, FPGA) or strong software development experience.

Education Requirements

MS or PhD in Computer Science or Computer Architecture (as listed in the original posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.