Power Management Architecture and Performance Modeling Engineer

Job Title

Power Management Architecture and Performance Modeling Engineer

Role Summary

Work on power management architecture and power/performance modeling for AMD Instinct AI/ML/HPC accelerators, spanning pre-silicon (concept-exit) to post-silicon (product launch) stages. The role supports setting and attaining performance-at-power targets through modeling, correlation, workload analysis, and methodology development.

Experience Level

Mid-level. No specific years-of-experience guidance provided in the posting.

Responsibilities

Primary responsibilities focus on modeling, architecture definition, cross-functional coordination, and post-silicon correlation to achieve power-constrained performance targets.

• Support power-constrained performance modeling, projections, target setting, and attainment tracking from pre-Si to post-Si for Instinct accelerators.
• Define and evaluate power management architecture across firmware, micro-architecture, macro-architecture, SoC, rack, and datacenter levels (e.g., SMU features, AVFS/RTAVFS, clock/power gating, p-states, on-die regulation).
• Develop and maintain power and performance models to support Cdyn/leakage/STA/area trade-off analysis and attainment.
• Create and apply ML-based modeling approaches (regression, gradient boosting, neural nets, etc.) to improve prediction accuracy, speed, and scalability across pre-Si and post-Si stages.
• Collaborate with product architecture and business teams to define product configurations and power/performance targets.
• Work cross-functionally with SOC architecture, system design, IP/circuit design, foundry, CAD, physical design, software, firmware, power management, and post-Si validation teams.
• Support post-silicon power/performance debug, calibration of pre-Si models against silicon, and correlation activities.
• Prepare power/performance roll-ups and readouts and drive awareness of power-efficiency improvements across teams.
• Contribute to workload power analysis and evolution of PPA methodologies.

Requirements

Must-have technical skills and constraints, plus desirable qualifications.

• Must-have: Background in computer architecture, processor/accelerator development, or power management architecture.
• Must-have: Experience or strong interest in power/performance modeling, projections, and optimization at SoC or system level.
• Must-have: Familiarity with digital logic physical design and power-management techniques (clock gating, power gating, V-F curves, p-states, on-die regulation, clock integrity).
• Must-have: Strong analytical skills and effective communication for cross-functional collaboration.
• Requirement: Must be eligible to work in Canada; this role is not eligible for visa sponsorship.
• Nice-to-have: Post-silicon power/performance debug and model correlation experience.
• Nice-to-have: Hands-on experience with machine learning model building or familiarity with ML fundamentals to develop ML-based power/perf models.
• Bonus: Knowledge of DL/ML/LLM/MoE workloads.

Education Requirements

Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.