Power Integrity Engineer - Silicon

Job Title

Power Integrity Engineer - Silicon

Role Summary

Senior-level power integrity engineer responsible for architecting and validating power delivery networks (PDNs) for 2.5D/3D heterogeneous packages that combine electrical ICs, photonic ICs, chiplets, and high-bandwidth memory.

The role leads cross-functional PI co-design with silicon, package, and photonics teams to enable low-noise, high-efficiency power for AI/HPC accelerators and supports qualification through to production.

Experience Level

Senior. Typical experience expectation: roughly 7+ to 10+ years of relevant industry experience in power integrity and advanced packaging.

Responsibilities

Primary responsibilities include architecting PDNs, performing analysis and validation, and collaborating across design and manufacturing teams.

• Define and implement PDN architectures for 2.5D/3D and chiplet-based designs, including on-package regulation and multi-rail topologies.
• Perform full-stack PI analysis: die-level IR drop/EM, package PDN impedance, transient response, and system-level validation.
• Model and simulate PDN behavior using industry PI tools and correlate simulation to lab measurements.
• Lead power integrity co-design for bump maps, power/ground grids, TSV/RDL routing, on-die decoupling, and regulator placement.
• Select and qualify power components and materials; collaborate with foundry/OSAT partners on manufacturability and yield.
• Develop PI methodologies, design rules, and sign-off criteria tailored to high-performance AI accelerators.
• Analyze and mitigate reliability risks including electromigration, thermal voltage droop, and power sequencing under dynamic workloads.
• Own lab qualification and validation using high-bandwidth scopes, VNAs, spectrum analyzers and correlate results to simulations.

Requirements

Must-have technical skills and experience; preferred items are listed separately.

• Deep expertise in power integrity for high-performance semiconductors: PDN design, frequency-domain and transient analysis, decoupling, IR drop/EM analysis, and noise mitigation.
• Proven track record in advanced packaging environments (2.5D/3D integration, interposers, FOWLP, CoWoS, hybrid bonding, or similar).
• Hands-on proficiency with PI simulation tools such as Ansys SIwave/HFSS, Cadence Sigrity, Apache RedHawk, Voltus, Keysight ADS, or equivalents, and demonstrated correlation to silicon measurements.
• Strong understanding of chip-package-system interactions, high-speed signaling impacts on PDN, and power-aware design for AI/HPC workloads.
• Experience driving cross-functional programs across silicon design, package engineering, system engineering, foundries, OSATs, and suppliers.
• Experience qualifying power components (VRMs, capacitors, inductors) and working with low-loss substrates and thermal materials.
• Clear communication, presentation, and documentation skills for influencing engineering stakeholders.

• Preferred: background in silicon photonics, CPO/NPO, photonic IC integration; familiarity with SerDes/PCIe/CXL, HBM, DTCO for 3D ICs, and multi-physics (thermal-electrical) co-design.

Education Requirements

Bachelor's degree in Electrical Engineering, Physics, or a related field with 10+ years of relevant industry experience; or Master's/PhD with 7+ years of related experience. Equivalent practical experience will be considered.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.