Power Integrity Engineer

Job Title

Power Integrity Engineer

Role Summary

Own the power integrity methodology for high-current PCB and system designs, ensuring robust power delivery to high-performance ASICs and supporting components from architecture through release. Member of the platform electrical engineering team focused on inference accelerator hardware.

On-site role based in San Jose (Santana Row); frequent collaboration with power design, PCB layout, ASIC/package, and mechanical teams.

Experience Level

Mid-level — typically requires 5+ years of hands-on power integrity experience on high-current, high-performance designs.

Responsibilities

Primary responsibilities include PDN analysis, DC/AC simulations, VRM modeling, thermal co-simulation, design-rule checks, and hardware bring-up support.

• Perform pre- and post-layout PDN analysis: target impedance profiling, decoupling capacitor selection and placement, and plane resonance analysis.
• Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation for PCB designers.
• Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the decoupling network.
• Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance versus ASIC power specs.
• Perform power-plane thermal co-simulation and coordinate thermal-electrical tradeoffs with mechanical teams.
• Drive design rule checks for PI compliance and work with layout teams using Cadence Allegro, Sigrity PowerDC/PowerSI, or Ansys SIwave.
• Support board bring-up, debug rail-level issues (droop, ripple, transient excursions), and document root cause and corrective actions.
• Develop and maintain simulation-to-hardware correlation databases to improve PDN modeling accuracy.

Requirements

Must-have technical skills and experience.

• 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms).
• Proficiency with PI EDA tools such as Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent.
• Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation.
• Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity.
• Working knowledge of VRM fundamentals: buck converter operation, multiphase design, transient response, and load-line/AVP concepts.
• Working knowledge of multi-layer PCB stack-up design and power plane allocation strategies.

Nice-to-have:

• Experience in data center, AI/ML accelerator, networking, or high-performance computing hardware environments.
• Experience with vertical power delivery, high-current lateral delivery tradeoffs, or 48V-to-point-of-load architectures.
• Package-level PDN co-analysis and experience using die/package power models from ASIC teams.
• Experience scripting automated PI simulation flows using Python or MATLAB.

Education Requirements

B.S. or M.S. in Electrical Engineering or a closely related discipline.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.