Power Infrastructure Engineer
SiFiveJob Title
Power Infrastructure Engineer
Role Summary
Develop and deploy methodology, tooling, and infrastructure to measure and analyze power consumption for SiFive IP. Work with architecture, RTL, and silicon teams to create power models and measurement systems that inform design and optimization decisions.
Experience Level
Senior — 8+ years of relevant experience in power benchmarking, analysis, and modeling.
Responsibilities
Key responsibilities include:
- Develop and deploy power analysis flows and models to collect and analyze power consumption data.
- Correlate power models and analysis with RTL and silicon measurements.
- Design and deploy power measurement infrastructure for lab and production validation.
- Create power models used for architecture exploration and design tradeoffs.
Requirements
Must-have skills and experience:
- 8+ years of experience in power benchmarking, analysis, and modeling.
- Experience analyzing power impacts at architecture, logic-design, and circuit levels.
- Knowledge of high-performance out-of-order CPU computer architecture.
- Experience with ASIC power analysis and optimization.
- Competency in software engineering best practices for maintaining and refactoring large object-oriented codebases.
- Self-starter with strong problem-solving skills and ability to learn quickly.
Nice-to-have:
- Hands-on expertise in hardware development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or software development.
Education Requirements
MS or PhD in Computer Science or Computer Architecture.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
