Power Design Engineer

Job Title

Power Design Engineer

Role Summary

Responsible for driving power analysis, projections, and optimisation for a CPU chiplet within a multi-chiplet System-in-Package. The role works across RTL, synthesis, and physical design teams and collaborates with SoC, board, and post-silicon groups.

Focus areas include CPU rail planning, system PDN optimisation, defining power vector plans, and correlating pre-silicon projections with silicon measurements.

Experience Level

Senior — typically 10+ years of ASIC or related design experience; candidates at various levels may be considered during interview but the role expects senior expertise.

Responsibilities

Primary responsibilities include defining and executing the power strategy for CPU chiplets and ensuring chip- and system-level power coverage throughout the design cycle.

• Own power analysis and projections for the CPU chiplet and chip-level power metrics.
• Define and maintain the power vector plan to provide comprehensive coverage across design iterations.
• Drive power analysis on RTL and netlist using tools such as Joules and PrimePower.
• Collaborate with RTL design, synthesis, and physical design teams to measure, optimise, and close power.
• Define CPU rail planning and optimise system power delivery network (PDN) for block rails.
• Evaluate and propose power-optimisation techniques at RTL, synthesis, and physical design stages; implement changes via timing ECOs and flow updates.
• Tabulate and compare power metrics and reports across design iterations.
• Work with post-silicon teams to correlate projections with silicon power measurements and update models.

Requirements

Must-have technical skills and experience to perform the role effectively; nice-to-have items indicate additional valuable skills.

• Must-have: Extensive experience in power analysis and optimisation for complex ASICs (typically 10+ years).
• Must-have: Hands-on experience across RTL, synthesis, and physical design stages, including low-power implementation techniques and ECO-based timing closure.
• Must-have: Proficiency with power-analysis tools such as Joules and PrimePower and scripting (Tcl plus at least one of Python or similar).
• Must-have: Strong analytical and problem-solving skills and clear written/verbal communication for cross-team collaboration.
• Nice-to-have: Familiarity with UPF/CPF low-power intent flows.
• Nice-to-have: Familiarity with Verilog/SystemVerilog and CPU microarchitecture power challenges.
• Nice-to-have: Basic thermal analysis experience.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.