Power Architect

Job Title

Power Architect

Role Summary

Responsible for defining and owning the shared power architecture and estimation framework for server-class AI accelerators. This role coordinates cross-functional tradeoffs across architecture, RTL, physical design, firmware, platform, and thermal teams to ensure power, performance, and deployability targets are met.

Experience Level

Mid-level (no explicit years of experience specified).

Responsibilities

The core responsibilities center on building power models, defining budgets and tradeoffs, and driving aligned decisions across the product lifecycle.

• Own the shared power architecture framework for server-class AI accelerators.
• Define power budgets, models, targets, and tradeoff methodologies.
• Build, correlate, and maintain estimation frameworks linking architectural intent to implementation results.
• Partner with architecture, RTL, DV, physical design, firmware, and platform teams.
• Surface, track, and drive cross-functional power tradeoffs during design and deployment.
• Advise on interactions among power, performance, area, timing, voltage, thermal, reliability, schedule, and deployability.
• Translate power assumptions and measurement data into actionable guidance for implementation teams.
• Help define power-control features, throttling policies, and telemetry requirements.

Requirements

Must-have technical skills and situational requirements.

• Proven experience in power architecture, power modeling, power methodology, or power-performance analysis for complex chips.
• Ability to reason across architecture, RTL, physical design, firmware, platform, and thermal constraints.
• Experience building both early-stage models to influence direction and later-stage models for correlation to implementation.
• Strong analytical skills for modeling, automation, and data analysis.
• Demonstrated judgment in ambiguous cross-functional decisions and credibility with senior technical counterparts.
• Effective communication skills to explain tradeoffs and drive alignment across teams.
• Authorization to work in the United States and ability to work from the Mountain View office Tuesdays–Thursdays.
• Ability to comply with U.S. export control requirements relevant to the role.

Nice-to-have:

• Experience with AI accelerators, GPUs, datacenter CPUs, networking silicon, or other server-class chips.
• Experience with ML workloads and performance-per-watt analysis.
• Experience correlating architectural models to RTL, physical design, silicon, or platform measurements.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.