PMTS ASIC Digital Design IP Engineering

Job Title

PMTS ASIC Digital Design IP Engineering

Role Summary

Lead architecture implementation, microarchitecture development, and RTL design for high-performance processor cores and subsystem components within ASIC/SoC teams. Collaborate with architecture, verification, physical design, DFT, firmware, and software teams to deliver products that meet performance, power, area, and schedule targets.

Experience Level

Senior — requires 12+ years of relevant experience in processor, CPU, DSP, or complex SoC digital design.

Responsibilities

The engineer will drive microarchitecture and RTL development, provide technical leadership, and coordinate cross-functional activities from design through silicon bring-up.

• Develop microarchitecture and implement RTL for CPU cores, caches, MMUs, interconnects, and system controllers.
• Translate architectural specifications into Verilog/SystemVerilog RTL and define block-level design specifications.
• Optimize designs for performance, power, and area; analyze latency, throughput, and scalability trade-offs.
• Lead critical processor design initiatives; mentor engineers and conduct architecture and RTL design reviews.
• Collaborate with verification, synthesis, timing, low-power, physical design, and DFT teams to close design cycles.
• Support silicon bring-up, debug, characterization, and production ramp activities.
• Perform performance analysis and drive microarchitectural enhancements to improve IPC, memory latency, and system efficiency.
• Perform duties in a safe and compliant manner following Environmental, Health, Safety & Security requirements.

Requirements

Must-have technical skills and experience:

• 12+ years of experience in processor, CPU, DSP, or complex SoC digital design.
• Deep understanding of processor microarchitecture: pipeline design, cache architectures, branch prediction, memory hierarchy, MMU/TLB, interrupts, and coherency protocols.
• Expert-level RTL design using Verilog/SystemVerilog.
• Strong knowledge of synthesis, timing analysis, CDC/RDC, and low-power design techniques.
• Experience with industry-standard EDA tools and design flows.
• Strong debugging and problem-solving skills.

Nice-to-have:

• Experience with RISC-V, ARM, MIPS, ARC, or custom CPU architectures.
• Knowledge of multi-core and heterogeneous computing systems, AI/ML acceleration, or vector processing.
• Experience with performance modeling, architectural simulation, and post-silicon debug.
• Exposure to safety-critical standards (ISO 26262, DO-254).

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.