PLL IC Design Engineer - TeraWave

Job Title

PLL IC Design Engineer - TeraWave

Role Summary

Design integrated Phase-Locked Loops (PLLs) and clocking systems for Blue Origin's TeraWave satellite communications program. Work on CMOS/FinFET analog/RF circuits to meet performance targets for phase noise, jitter, power, and integration into SoC/RF subsystems.

This onsite role will be based in San Diego, the Bay Area, or Renton; relocation is provided and travel is expected up to 10%.

Experience Level

Senior-level - 7+ years of relevant PLL/clocking integrated circuit design experience.

Responsibilities

Primary responsibilities include end-to-end PLL and clocking circuit development, integration, and validation for space-communications ASICs.

• Lead system and circuit design of PLLs and clock distribution circuits in advanced CMOS (FinFET) technologies, optimizing phase noise/jitter, power, and area trade-offs.
• Perform mixed-signal design and verification using Spectre, AMS flows, MATLAB, and SystemVerilog models.
• Define PLL and sub-block requirements with RF and SoC system architects and chip leads.
• Oversee layout, top-level integration, floorplanning, and verification through tape-out.
• Develop test plans with validation and product engineers; support silicon bring-up, characterization, debugging, and yield optimization.
• Investigate and implement analog building blocks to improve circuit performance.
• Mentor junior engineers on analog/PLL design best practices.

Requirements

Required technical skills, experience, and eligibility for employment.

Must-have:

• 7+ years designing fractional-N PLLs, DLLs, and related sub-circuits in FinFET CMOS nodes (7nm or more advanced).
• Extensive experience with PLL building blocks: VCOs, high-speed integer and fractional-N prescalers, PFDs, charge pumps, etc.
• Experience with clock domain synchronization and clock distribution design (clock trees, frequency multipliers/dividers, CML buffers, inductive peaking).
• Proficiency in mixed-mode modeling, simulation, and verification using MATLAB, Spectre, SystemVerilog, and AMS flows.
• Extensive experience in PLL silicon characterization and debugging.
• Proficiency designing fundamental analog/RF blocks: amplifiers, filters, clock buffers, bias generators.
• Must be a U.S. citizen or national, U.S. permanent resident (Green Card), or lawfully admitted into the U.S. as a refugee or granted asylum.

Nice-to-have:

• Experience with All-Digital PLLs (ADPLL) and sub-sampling PLLs.
• Expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.
• Experience with LDOs, operational amplifiers, and device-physics-driven process selection.
• Familiarity with digital design, digital verification, and SystemVerilog modeling.

Education Requirements

Bachelor's degree in Electrical Engineering or a related technical discipline is required. Advanced degree (MS or PhD) in Electrical Engineering or a related field is preferred.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.