Place and Route Design Automation Engineer

Job Title

Place and Route Design Automation Engineer

Role Summary

Senior engineer on the Design Methodology and Automation team responsible for development and support of automated place-and-route (P&R) tools, flows, and methodologies for next-generation FPGA silicon.

Work cross-functionally with physical design, CAD, RTL, and synthesis teams to improve quality of results (timing, power, congestion, density), runtime efficiency, and flow robustness.

Experience Level

Senior — requires 7+ years of industry experience in semiconductor design or design automation.

Responsibilities

Key responsibilities include:

• Develop and maintain P&R tools, automation flows, and infrastructure for FPGA silicon design.
• Design and implement new methodologies and tool enhancements for next-generation P&R flows.
• Provide end-user support: debug issues, triage flow failures, and promote best practices.
• Create and enhance scripts and automation utilities to improve usability, efficiency, and scalability.
• Drive improvements in P&R quality of results: timing, power, congestion, density, and design closure.
• Evaluate and test new P&R tool capabilities and methodologies.
• Identify flow or design bottlenecks and implement practical optimizations.
• Collaborate with multi-geo teams across physical design, RTL, synthesis, and CAD to ensure robust end-to-end flow support.
• Document methodologies, flow updates, and usage guidelines.

Requirements

Must-have skills and experience:

• 7+ years hands-on experience in Place & Route, physical design, or design automation within FPGA or ASIC development environments.
• Extensive experience using industry-standard EDA P&R tools (e.g., Synopsys, Cadence) in production design flows.
• Strong scripting and coding skills: Tcl, Perl, and Python for automation and tool integration.
• Proficient in Unix/Linux development and tooling.
• Applied knowledge of physical design fundamentals: floorplanning, placement, clocking, routing, and static timing analysis.
• Proven ability to debug and resolve tool, flow, or design issues in a collaborative environment.
• Experience collaborating with cross-functional and geographically distributed engineering teams.

Nice-to-have:

• Experience improving timing, power, or congestion on advanced FPGA silicon nodes.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting specifies 7+ years of industry experience in semiconductor design or design automation.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.