Physical Verification & Signoff Engineer

Job Title

Physical Verification & Signoff Engineer

Role Summary

The Physical Verification & Signoff Engineer is responsible for final signoff of tapeouts, owning physical verification and reliability checks for production silicon programs. The role works with physical design teams and foundries and contributes to automation and AI-assisted signoff workflows.

Experience Level

Mid-level. The posting requests 5+ years of physical verification or signoff experience (typical mid-career range: 3–7 years).

Responsibilities

Primary responsibilities include signoff verification, reliability analysis, debugging, and automation:

• Perform DRC, LVS, ERC, and antenna signoff at block and full-chip levels.
• Run and sign off IR drop, electromigration (EM), and power integrity analyses.
• Debug signoff violations and drive fixes with physical design teams.
• Manage tapeout checklists and prepare foundry deliverables.
• Build automation for signoff runs, triage, and reporting.
• Collaborate on defining how AI can triage and remediate signoff issues.

Requirements

Must-have technical skills and experience; followed by desirable additions.

Must-have:

• 5+ years of physical verification or signoff experience on production tapeouts.
• Deep experience with Calibre or IC Validator.
• Experience with RedHawk or Voltus (IR/EM analysis).
• Strong understanding of foundry rule decks at advanced nodes.
• Experience scripting in Tcl, Python, or SVRF.

Nice-to-have:

• Experience with 2.5D/3D packaging or chiplet integration signoff.
• Direct foundry interface experience.
• Interest or experience with AI-assisted design tools.

Education Requirements

Not specified.

About the Company

Company: Voltai

Headquarters: Palo Alto, CA, United States

Voltai develops AI-driven world models and agents to design, evaluate, and optimize physical systems-focusing on hardware, electronics, and semiconductors to enable AI-led hardware co-design, performance modeling, and cross-domain optimization.