Physical Design Staff Engineer
SynopsysJob Title
Physical Design Staff Engineer
Role Summary
Senior physical-design engineer responsible for timing closure, signoff readiness, and PPA optimization for advanced-node ASIC designs. Work spans block, subsystem, and chip-level implementation and focuses on building reusable methodologies and automation to improve design predictability and reduce cycle time.
Experience Level
Senior - typically requires 5+ years of hands-on ASIC physical-design experience.
Responsibilities
Primary responsibilities include driving implementation quality, developing automation, and troubleshooting complex physical-design issues.
- Drive timing closure, signoff readiness, and PPA optimization across block, subsystem, and chip-level designs.
- Develop and enhance physical-design methodologies and automation using TCL, Python, Perl, Pandas, or similar tools.
- Perform static timing analysis, clock-tree synthesis, and ECO implementation with tools such as PrimeTime, ICC2, Fusion Compiler, or Cadence Innovus.
- Analyze design data and trends to identify bottlenecks and build reusable flows that improve subsequent tapeouts.
- Collaborate with design, verification, and CAD teams to ensure successful silicon delivery.
- Contribute to AI/ML-assisted design optimization and data-driven engineering initiatives.
- Troubleshoot complex physical-design corner cases and develop scalable technical solutions.
Requirements
Must-have technical skills and experience; preferred items noted.
- 5+ years of hands-on ASIC physical-design, implementation, and timing-closure experience at block, subsystem, or chip level.
- Deep working knowledge of static timing analysis (STA), clock-tree synthesis (CTS), signoff flows, and ECO methodologies.
- Proficiency with industry implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus.
- Strong scripting and automation skills (TCL, Python, Perl, or similar) for flow development and data analysis.
- Ability to diagnose root causes from timing reports and implement methodology-level fixes rather than ad hoc changes.
- Experience working independently across global teams and communicating technical tradeoffs clearly.
- Preferred: experience with advanced-node semiconductor design (7nm or below) and exposure to ML/AI-assisted optimization.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
